fix 2
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parent
b95fa4ca11
commit
00c46e16e9
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@ -8,7 +8,7 @@ Config::Config(char *argv[])
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L1_assoc = atoi(argv[4]);
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L2_assoc = atoi(argv[5]);
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victimCacheSize = atoi(argv[6]);
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trace_file = std::string(argv[7]);
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fileName = std::string(argv[7]);
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}
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void Config::printConfig()
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@ -21,7 +21,7 @@ void Config::printConfig()
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cout << setw(30) << "Victim_Cache_SIZE:" << this->victimCacheSize << endl;
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cout << setw(30) << "L2_SIZE:" << this->L2_size << endl;
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cout << setw(30) << "L2_ASSOC:" << this->L2_assoc << endl;
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cout << setw(30) << "trace_file:" << this->trace_file << endl;
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cout << setw(30) << "trace_file:" << this->fileName << endl;
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cout << "===================================" << endl;
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}
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@ -30,21 +30,20 @@ NewCache::NewCache(Config *config)
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this->config = config;
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if (config->L2_size > 0)
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{
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Cache *L2 = new Cache(config->blockSize, config->L2_size, config->L2_assoc, 0, "L2");
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cache = new Cache(config->blockSize, config->L1_size, config->L1_assoc, config->victimCacheSize, L2, "L1");
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l1 = cache, l2 = L2;
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Has2 = config->L2_size, HasV = config->victimCacheSize;
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l2 = new Cache(config->blockSize, config->L2_size, config->L2_assoc, 0, "L2");
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l1 = new Cache(config->blockSize, config->L1_size, config->L1_assoc, config->victimCacheSize, l2, "L1");
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isL2Exist = config->L2_size, isVictimExist = config->victimCacheSize;
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}
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else
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{
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cache = new Cache(config->blockSize, config->L1_size, config->L1_assoc, config->victimCacheSize, nullptr, "L1");
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l1 = cache, l2 = nullptr;
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Has2 = config->L2_size, HasV = config->victimCacheSize;
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l2 = nullptr;
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l1 = new Cache(config->blockSize, config->L1_size, config->L1_assoc, config->victimCacheSize, nullptr, "L1");
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isL2Exist = config->L2_size, isVictimExist = config->victimCacheSize;
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}
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}
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void NewCache::printMonitor()
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void NewCache::printNewCache()
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{
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cout << "====== Simulation results (raw) ======" << endl;
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cout << setw(38) << "a. number of L1 reads: " << this->l1->r << endl;
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@ -53,14 +52,14 @@ void NewCache::printMonitor()
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cout << setw(38) << "d. number of L1 write misses: " << this->l1->wm << endl;
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cout << setw(38) << "e. L1 miss rate: " << fixed << setprecision(4) << this->l1->getMR() << endl;
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cout << setw(38) << "f. number of swaps: " << this->l1->ex << endl;
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cout << setw(38) << "g. number of victim cache writeback: " << (this->HasV ? this->l1->wb : 0) << endl;
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if (this->Has2)
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cout << setw(38) << "g. number of victim cache writeback: " << (this->isVictimExist ? this->l1->wb : 0) << endl;
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if (this->isL2Exist)
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{
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cout << setw(38) << "h. number of L2 reads: " << this->l2->r << endl;
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cout << setw(38) << "i. number of L2 read misses: " << this->l2->rm << endl;
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cout << setw(38) << "j. number of L2 writes: " << this->l2->w << endl;
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cout << setw(38) << "k. number of L2 write misses: " << this->l2->wm << endl;
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cout << setw(38) << "l. L2 miss rate: " << fixed << setprecision((this->Has2) ? 4 : 0) << this->l2->getMR2() << endl;
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cout << setw(38) << "l. L2 miss rate: " << fixed << setprecision((this->isL2Exist) ? 4 : 0) << this->l2->getMR2() << endl;
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cout << setw(38) << "m. number of L2 writebacks: " << this->l2->wb << endl;
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cout << setw(38) << "n. total memory traffic: " << (this->l2->rm + this->l2->wm + this->l2->wb) << endl;
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cout << "==== Simulation results (performance) ====" << endl;
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@ -16,7 +16,7 @@ public:
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int L1_assoc;
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int L2_assoc;
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int victimCacheSize;
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string trace_file;
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string fileName;
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Config(char *argv[]);
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void printConfig();
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@ -26,11 +26,10 @@ class NewCache
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{
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public:
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Config *config;
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Cache *cache;
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Cache *l1, *l2;
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bool Has2, HasV;
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bool isL2Exist, isVictimExist;
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NewCache(Config *config);
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void printMonitor();
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void printNewCache();
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};
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Binary file not shown.
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@ -80,7 +80,7 @@ void CacheConfig::setupTIO()
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// vim = ((1<<vi)-1) << vo;
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}
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CacheTIO CacheConfig::VictimAddrParser(uint32_t addr)
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CacheIndex CacheConfig::VictimAddrParser(uint32_t addr)
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{
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uint32_t offset = addr & vom;
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// uint32_t index = (addr & vim) >> vo;
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@ -88,7 +88,7 @@ CacheTIO CacheConfig::VictimAddrParser(uint32_t addr)
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return {tag, 0, offset, addr};
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}
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CacheTIO CacheConfig::AddrParser(uint32_t addr)
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CacheIndex CacheConfig::AddrParser(uint32_t addr)
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{
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uint32_t offset = addr & om;
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uint32_t index = (addr & im) >> o;
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@ -96,16 +96,15 @@ CacheTIO CacheConfig::AddrParser(uint32_t addr)
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return {tag, index, offset, addr};
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}
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uint32_t CacheConfig::UnParser(uint32_t tag, CacheTIO tio)
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uint32_t CacheConfig::UnParser(uint32_t tag, CacheIndex tio)
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{
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return (tag << (o + i)) | (tio.index << o) | (tio.offset);
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}
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uint32_t CacheConfig::UnParserVic(uint32_t tag, CacheTIO tio)
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uint32_t CacheConfig::UnParserVic(uint32_t tag, CacheIndex tio)
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{
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return (tag << (vo)) | (tio.offset);
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}
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Cache::Cache(int blockSize, int s, int assoc, int victimSize, string l, int replicementPolicy, int writePolicy)
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{
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@ -323,3 +322,27 @@ void Cache::printCache()
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}
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}
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double Cache::getMR()
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{
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return (double)(rm + wm) / (double)(r + w);
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}
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double Cache::getMR2()
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{
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return (double)(rm) / (double)(r);
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}
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double Cache::getAAT()
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{
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double HT = config.getHT();
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double MP = config.getMP();
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double MR = getMR();
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return HT + (MP * MR);
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}
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void Cache::Read() { r++; }
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void Cache::ReadMiss() { rm++; }
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void Cache::Write() { w++; }
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void Cache::WriteMiss() { wm++; }
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void Cache::WriteBack() { wb++; }
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void Cache::Exchange() { ex++; }
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int Cache::getCommunication() { return rm + wm + wb; }
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@ -8,7 +8,7 @@
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#include <ostream>
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#include <vector>
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using namespace std;
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struct CacheTIO
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struct CacheIndex
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{
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uint32_t tag, index, offset, rAddr;
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};
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@ -50,10 +50,10 @@ public:
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uint32_t getVictimAs();
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uint32_t getAs();
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void setupTIO();
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CacheTIO VictimAddrParser(uint32_t addr);
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CacheTIO AddrParser(uint32_t addr);
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uint32_t UnParser(uint32_t tag, CacheTIO tio);
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uint32_t UnParserVic(uint32_t tag, CacheTIO tio);
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CacheIndex VictimAddrParser(uint32_t addr);
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CacheIndex AddrParser(uint32_t addr);
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uint32_t UnParser(uint32_t tag, CacheIndex tio);
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uint32_t UnParserVic(uint32_t tag, CacheIndex tio);
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int getBlockSize();
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int Size();
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int Assoc();
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@ -70,7 +70,6 @@ struct Block
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bool operator<(const Block &t) const { return lru < t.lru; }
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};
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class Cache
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{
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public:
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@ -80,10 +79,8 @@ public:
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vector<Block> vc; // Victim Cache
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string level;
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Cache *NextCache = nullptr;
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int r = 0; // Read Count
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int rm = 0; // Read Miss
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int w = 0; // Write Count
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@ -91,33 +88,18 @@ public:
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int wb = 0; // Write Back
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int ex = 0; // Exchange (between L1 and Victim)
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void Read() { r++; }
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void ReadMiss() { rm++; }
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void Write() { w++; }
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void WriteMiss() { wm++; }
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void WriteBack() { wb++; }
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void Exchange() { ex++; }
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int getCommunication() { return rm + wm + wb; }
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double getMR()
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{
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return (double)(rm + wm) / (double)(r + w);
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}
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double getMR2()
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{
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return (double)(rm) / (double)(r);
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}
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double getAAT()
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{
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double HT = config.getHT();
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double MP = config.getMP();
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double MR = getMR();
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return HT + (MP * MR);
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}
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void Read();
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void ReadMiss();
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void Write();
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void WriteMiss();
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void WriteBack();
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void Exchange();
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int getCommunication();
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double getMR();
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double getMR2();
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double getAAT();
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Cache(int blockSize, int s, int assoc, int victimSize, string l = "L1", int replicementPolicy = LRU, int writePolicy = LFU);
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Cache(int blockSize, int s, int assoc, int victimSize, Cache *n = nullptr, string l = "L1", int replicementPolicy = LRU, int writePolicy = LFU);
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Binary file not shown.
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@ -19,13 +19,13 @@ int main(int argc, char *argv[])
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try
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{
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ifstream trace("../traces/" + config->trace_file);
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ifstream trace("../traces/" + config->fileName);
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string line;
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char op;
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unsigned addr;
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while (getline(trace, line) && (istringstream(line) >> op >> hex >> addr))
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{
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newCache->cache->useCache(addr, op == 'w');
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newCache->l1->useCache(addr, op == 'w');
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}
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trace.close();
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}
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@ -38,10 +38,10 @@ int main(int argc, char *argv[])
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try
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{
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config->printConfig();
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newCache->cache->printCache();
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if (newCache->Has2)
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(newCache->cache->NextCache)->printCache();
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newCache->printMonitor();
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newCache->l1->printCache();
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if (newCache->isL2Exist)
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newCache->l2->printCache();
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newCache->printNewCache();
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}
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catch (...)
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{
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