fix 6
This commit is contained in:
parent
c03fafcf95
commit
52ac2e49dc
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===== Simulator configuration =====
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BLOCKSIZE: 32
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L1_SIZE: 2048
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L1_ASSOC: 4
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Victim_Cache_SIZE: 0
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L2_SIZE: 4096
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L2_ASSOC: 8
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trace_file: gcc_trace.txt
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===================================
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===== L1 contents =====
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set 0: 20028d D 20018a 20028e D 200198 D
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set 1: 2001c1 D 20028d D 200153 D 20013b
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set 2: 200223 D 20028d D 200241 2001c1
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set 3: 20018a 2001ac D 20028e D 20028d D
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set 4: 20018f D 2000f9 20017a D 20018a
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set 5: 200009 20017a 2000fa 20018a
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set 6: 200009 2000f9 20028d D 20018a
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set 7: 200009 2001ac 2000fa 200149
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set 8: 200009 3d819c D 20017b D 2000f9
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set 9: 200009 2000fa 2000f9 2001b2 D
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set 10: 200009 200214 2000fa 20023f
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set 11: 200009 2001ab 20013a 20023f
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set 12: 20018f D 2001f2 2001aa 20018a D
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set 13: 20028d D 20018d D 20013a 20028c D
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set 14: 20013a 20018d D 20028d D 2001ad D
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set 15: 2001f8 D 20028c D 20013a 20018d D
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===== L2 contents =====
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set 0: 20018a 20028e 200198 2001ab 2001d1 D 20017a D 20028d 2001f4 D
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set 1: 2001c1 200153 D 20028e D 20013b 200198 D 2000fb 2001d1 D 20028d
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set 2: 200241 20028d D 200223 200149 200198 D 20018a 2001c1 D 20013b
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set 3: 2001ac 2001c1 D 20028e 2001b0 D 20028d 20028c D 20018a 2001bd D
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set 4: 2000f9 20028e D 20018a 20028d D 20017a D 20023f 200149 2002b1 D
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set 5: 20017a 20028e D 200009 20028d D 2000fa 2001b2 D 20018a 20023f
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set 6: 200009 2000f9 2001b2 D 20023f 2001ac D 2001ad D 20028d 20028c D
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set 7: 200009 20028d D 2000fa 2001b2 D 2001ac 20023f 200149 2001f6 D
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set 8: 200009 20017b D 2000fa 2001b2 D 2000f9 20028d D 20023f 200149
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set 9: 200009 2000fa 20028d D 2001b2 20023f 3d819c D 20028c D 2001aa
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set 10: 200009 200214 D 20028d D 20023f 2001ab D 2001aa 2001fc D 2000fa
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set 11: 200009 2001ab 20028d D 20023f 2001aa 200214 D 20028c D 20013a
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set 12: 20018f 2001aa 20018a 2001f2 20023f 20028d D 20018d D 2001ab
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set 13: 20028d 2001b3 D 20018d 2001ab D 20013a 2001b2 D 20028c 2001fe D
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set 14: 20028d 20028c D 20018d 2001a7 D 20013a 2001b2 D 2001ad D 2001fd D
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set 15: 20013a 20028d D 20018d 200197 D 2001f8 2001a9 D 200222 D 2001d1 D
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====== Simulation results (raw) ======
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a. number of L1 reads: 63640
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b. number of L1 read misses: 5170
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c. number of L1 writes: 36360
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d. number of L1 write misses: 4452
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e. L1 miss rate: 0.0962
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f. number of swaps: 0
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g. number of victim cache writeback: 0
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h. number of L2 reads: 9622
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i. number of L2 read misses: 5313
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j. number of L2 writes: 4942
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k. number of L2 write misses: 151
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l. L2 miss rate: 0.5522
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m. number of L2 writebacks: 2978
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n. total memory traffic: 8442
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==== Simulation results (performance) ====
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1. average access time: 1.7920 ns
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@ -1,164 +0,0 @@
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===== Simulator configuration =====
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BLOCKSIZE: 16
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L1_SIZE: 1024
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L1_ASSOC: 8
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Victim_Cache_SIZE: 0
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L2_SIZE: 8192
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L2_ASSOC: 4
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trace_file: go_trace.txt
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===================================
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===== L1 contents =====
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set 0: 800470 D 80046f D 80046e D 80046d D 80046c D 80046b D 80046a D 800469 D
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set 1: 800470 D 80046f D 80046e D 80046d D 80046c D 80046b D 80046a D 800469 D
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set 2: 800470 D 80046f D 80046e D 80046d D 80046c D 80046b D 80046a D 800469 D
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set 3: 800470 D 80046f D 80046e D 80046d D 80046c D 80046b D 80046a D 800469 D
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set 4: 800470 D 80046f D 80046e D 80046d D 80046c D 80046b D 80046a D 800469 D
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set 5: 80046f D 80046e D 80046d D 80046c D 80046b D 80046a D 800469 D 800468 D
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set 6: 80046f D 80046e D 80046d D 80046c D 80046b D 80046a D 800469 D 800468 D
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set 7: 80046f D 80046e D 80046d D 80046c D 80046b D 80046a D 800469 D 800468 D
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===== L2 contents =====
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set 0: 80047 80046 D 80045 D 80044 D
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set 1: 80047 80046 D 80045 D 80044 D
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set 2: 80047 80046 D 80045 D 80044 D
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set 3: 80047 80046 D 80045 D 80044 D
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set 4: 80047 80046 D 80045 D 80044 D
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set 5: 80046 D 80045 D 80044 D 80043 D
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set 6: 80046 D 80045 D 80044 D 80043 D
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set 7: 80046 D 80045 D 80044 D 80043 D
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set 8: 80046 D 80045 D 80044 D 80043 D
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set 9: 80046 D 80045 D 80044 D 80043 D
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set 10: 80046 D 80045 D 80044 D 80043 D
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set 11: 80046 D 80045 D 80044 D 80043 D
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set 12: 80046 D 80045 D 80044 D 80043 D
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set 13: 80046 D 80045 D 80044 D 80043 D
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set 14: 80046 D 80045 D 80044 D 80043 D
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set 15: 80046 D 80045 D 80044 D 80043 D
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set 16: 80046 D 80045 D 80044 D 80043 D
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set 17: 80046 D 80045 D 80044 D 80043 D
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set 18: 80046 D 80045 D 80044 D 80043 D
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set 19: 80046 D 80045 D 80044 D 80043 D
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set 20: 80046 D 80045 D 80044 D 80043 D
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set 21: 80046 D 80045 D 80044 D 80043 D
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set 22: 80046 D 80045 D 80044 D 80043 D
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set 23: 80046 D 80045 D 80044 D 80043 D
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set 24: 80046 D 80045 D 80044 D 80043 D
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set 25: 80046 D 80045 D 80044 D 80043 D
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set 26: 80046 D 80045 D 80044 D 80043 D
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set 27: 80046 D 80045 D 80044 D 80043 D
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set 28: 80046 D 80045 D 80044 D 80043 D
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set 29: 80046 D 80045 D 80044 D 80043 D
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set 30: 80046 D 80045 D 80044 D 80043 D
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set 31: 80046 D 80045 D 80044 D 80043 D
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set 32: 80046 D 80045 D 80044 D 80043 D
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set 33: 80046 D 80045 D 80044 D 80043 D
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set 34: 80046 D 80045 D 80044 D 80043 D
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set 35: 80046 D 80045 D 80044 D 80043 D
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set 36: 80046 D 80045 D 80044 D 80043 D
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set 37: 80046 D 80045 D 80044 D 80043 D
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set 38: 80046 D 80045 D 80044 D 80043 D
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set 39: 80046 D 80045 D 80044 D 80043 D
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set 40: 80046 D 80045 D 80044 D 80043 D
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set 41: 80046 D 80045 D 80044 D 80043 D
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set 42: 80046 D 80045 D 80044 D 80043 D
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set 43: 80046 D 80045 D 80044 D 80043 D
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set 44: 80046 D 80045 D 80044 D 80043 D
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set 45: 80046 D 80045 D 80044 D 80043 D
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set 46: 80046 D 80045 D 80044 D 80043 D
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set 47: 80046 D 80045 D 80044 D 80043 D
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set 48: 80046 D 80045 D 80044 D 80043 D
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set 49: 80046 D 80045 D 80044 D 80043 D
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set 50: 80046 D 80045 D 80044 D 80043 D
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set 51: 80046 D 80045 D 80044 D 80043 D
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set 52: 80046 D 80045 D 80044 D 80043 D
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set 53: 80046 D 80045 D 80044 D 80043 D
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set 54: 80046 D 80045 D 80044 D 80043 D
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set 55: 80046 D 80045 D 80044 D 80043 D
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set 56: 80046 D 80045 D 80044 D 80043 D
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set 57: 80046 D 80045 D 80044 D 80043 D
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set 58: 80046 D 80045 D 80044 D 80043 D
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set 59: 80046 D 80045 D 80044 D 80043 D
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set 60: 80046 D 80045 D 80044 D 80043 D
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set 61: 80046 D 80045 D 80044 D 80043 D
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set 62: 80046 D 80045 D 80044 D 80043 D
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set 63: 80046 D 80045 D 80044 D 80043 D
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set 64: 80046 D 80045 D 80044 D 80043 D
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set 65: 80046 D 80045 D 80044 D 80043 D
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set 66: 80046 D 80045 D 80044 D 80043 D
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set 67: 80046 D 80045 D 80044 D 80043 D
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set 68: 80046 D 80045 D 80044 D 80043 D
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set 69: 80046 80045 D 80044 D 80043 D
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set 70: 80046 80045 D 80044 D 80043 D
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set 71: 80046 80045 D 80044 D 80043 D
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set 72: 80046 80045 D 80044 D 80043 D
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set 73: 80046 80045 D 80044 D 80043 D
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set 74: 80046 80045 D 80044 D 80043 D
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set 75: 80046 80045 D 80044 D 80043 D
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set 76: 80046 80045 D 80044 D 80043 D
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set 77: 80046 80045 D 80044 D 80043 D
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set 78: 80046 80045 D 80044 D 80043 D
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set 79: 80046 80045 D 80044 D 80043 D
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set 80: 80046 80045 D 80044 D 80043 D
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set 81: 80046 80045 D 80044 D 80043 D
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set 82: 80046 80045 D 80044 D 80043 D
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set 83: 80046 80045 D 80044 D 80043 D
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set 84: 80046 80045 D 80044 D 80043 D
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set 85: 80046 80045 D 80044 D 80043 D
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set 86: 80046 80045 D 80044 D 80043 D
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set 87: 80046 80045 D 80044 D 80043 D
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set 88: 80046 80045 D 80044 D 80043 D
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set 89: 80046 80045 D 80044 D 80043 D
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set 90: 80046 80045 D 80044 D 80043 D
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set 91: 80046 80045 D 80044 D 80043 D
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set 92: 80046 80045 D 80044 D 80043 D
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set 93: 80046 80045 D 80044 D 80043 D
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set 94: 80046 80045 D 80044 D 80043 D
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set 95: 80046 80045 D 80044 D 80043 D
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set 96: 80046 80045 D 80044 D 80043 D
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set 97: 80046 80045 D 80044 D 80043 D
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set 98: 80046 80045 D 80044 D 80043 D
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set 99: 80046 80045 D 80044 D 80043 D
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set 100: 80046 80045 D 80044 D 80043 D
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set 101: 80046 80045 D 80044 D 80043 D
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set 102: 80046 80045 D 80044 D 80043 D
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set 103: 80046 80045 D 80044 D 80043 D
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set 104: 80046 80045 D 80044 D 80043 D
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set 105: 80046 80045 D 80044 D 80043 D
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set 106: 80046 80045 D 80044 D 80043 D
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set 107: 80046 80045 D 80044 D 80043 D
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set 108: 80046 80045 D 80044 D 80043 D
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set 109: 80046 80045 D 80044 D 80043 D
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set 110: 80046 80045 D 80044 D 80043 D
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set 111: 80046 80045 D 80044 D 80043 D
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set 112: 80046 80045 D 80044 D 80043 D
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set 113: 80046 80045 D 80044 D 80043 D
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set 114: 80046 80045 D 80044 D 80043 D
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set 115: 80046 80045 D 80044 D 80043 D
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set 116: 80046 80045 D 80044 D 80043 D
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set 117: 80046 80045 D 80044 D 80043 D
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set 118: 80046 80045 D 80044 D 80043 D
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set 119: 80046 80045 D 80044 D 80043 D
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set 120: 80046 80045 D 80044 D 80043 D
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set 121: 80046 80045 D 80044 D 80043 D
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set 122: 80046 80045 D 80044 D 80043 D
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set 123: 80046 80045 D 80044 D 80043 D
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set 124: 80046 80045 D 80044 D 80043 D
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set 125: 80046 80045 D 80044 D 80043 D
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set 126: 80046 80045 D 80044 D 80043 D
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set 127: 80046 80045 D 80044 D 80043 D
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====== Simulation results (raw) ======
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a. number of L1 reads: 60613
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b. number of L1 read misses: 3819
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c. number of L1 writes: 39387
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d. number of L1 write misses: 6341
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e. L1 miss rate: 0.1016
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f. number of swaps: 0
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g. number of victim cache writeback: 0
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h. number of L2 reads: 10160
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i. number of L2 read misses: 9847
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j. number of L2 writes: 8323
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k. number of L2 write misses: 3
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l. L2 miss rate: 0.9692
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m. number of L2 writebacks: 7869
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n. total memory traffic: 17719
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==== Simulation results (performance) ====
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1. average access time: 2.7692 ns
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===== Simulator configuration =====
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BLOCKSIZE: 32
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L1_SIZE: 1024
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L1_ASSOC: 8
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Victim_Cache_SIZE: 256
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L2_SIZE: 0
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L2_ASSOC: 0
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trace_file: perl_trace.txt
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===================================
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===== L1 contents =====
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set 0: 8003d7 80037c D 800276 D 8003d8 800379 800368 f6067b D 8003d9
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set 1: 80056c 800045 80058c 8003d7 8002c1 D 800379 8003d8 80037b
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set 2: 800045 80058c D 8003d2 800379 D f6067d D 80018e 8003d8 f60677
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set 3: 800580 8003d1 f6067d D 800325 80018e 8003d8 8003d2 D 800276
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===== Victim Cache contents =====
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set 0: 2000f4f 3d819ed D 20006a2 D 20009da 3d819dd 20006a1 20006a5 D 2000f4c D
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====== Simulation results (raw) ======
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a. number of L1 reads: 70107
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b. number of L1 read misses: 14002
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c. number of L1 writes: 29893
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d. number of L1 write misses: 4835
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e. L1 miss rate: 0.1884
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f. number of swaps: 4060
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g. number of victim cache writeback: 6735
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h. number of L2 reads: 0
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i. number of L2 read misses: 0
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j. number of L2 writes: 0
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k. number of L2 write misses: 0
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l. L2 miss rate: 0
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m. number of L2 writebacks: 0
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n. total memory traffic: 25572
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==== Simulation results (performance) ====
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1. average access time: 4.4607 ns
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===== Simulator configuration =====
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BLOCKSIZE: 128
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L1_SIZE: 1024
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L1_ASSOC: 2
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Victim_Cache_SIZE: 1024
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L2_SIZE: 4096
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L2_ASSOC: 4
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trace_file: gcc_trace.txt
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===================================
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===== L1 contents =====
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set 0: 2001c1 D 20028d D
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set 1: 200009 20017a
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set 2: 200009 200214
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set 3: 2001f8 D 20028c D
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===== Victim Cache contents =====
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set 0: f60672 D 80063d D 80088c D 800904 8006b1 800628 8006ae 80063f D
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===== L2 contents =====
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set 0: 1000c5 1000d6 D 100147 D 1000cc D
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set 1: 1000bd D 100147 D 10007d 1000d6
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set 2: 10010a 1000d9 D 10009d 10007d
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set 3: 1000fc D 1000c5 D 1000d5 10009d
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set 4: 1000a9 D 100120 100111 100146 D
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set 5: 100004 10007c 1000c7 D 100146 D
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set 6: 100004 1000bd D 1000d5 10007c
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set 7: 1000c7 1000d5 1000c6 D 10011f
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====== Simulation results (raw) ======
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a. number of L1 reads: 63640
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b. number of L1 read misses: 8160
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c. number of L1 writes: 36360
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d. number of L1 write misses: 3824
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e. L1 miss rate: 0.1198
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f. number of swaps: 9722
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g. number of victim cache writeback: 4763
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h. number of L2 reads: 11984
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i. number of L2 read misses: 7690
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j. number of L2 writes: 4763
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k. number of L2 write misses: 1205
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l. L2 miss rate: 0.6417
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m. number of L2 writebacks: 3198
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n. total memory traffic: 12093
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==== Simulation results (performance) ====
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1. average access time: 2.6884 ns
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===== Simulator configuration =====
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BLOCKSIZE: 64
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L1_SIZE: 8192
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L1_ASSOC: 2
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Victim_Cache_SIZE: 1024
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L2_SIZE: 16384
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L2_ASSOC: 4
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trace_file: perl_trace.txt
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===================================
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===== L1 contents =====
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set 0: 4002d D 4002c D
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set 1: 4002c D 4002d D
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set 2: 40016 D 4002d D
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set 3: 4002d D 4002c D
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set 4: 4002d D 4001d D
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set 5: 4002a 4002c D
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set 6: 4002b D 4002c D
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set 7: 4001d 4002c D
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set 8: 4000f D 4002c D
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set 9: 40011 D 4002c D
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set 10: 40002 4002c D
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set 11: 40002 40019
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set 12: 4002c D 40028
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set 13: 40013 D 4002b
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set 14: 40013 D 4002c
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set 15: 4001d 40028
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set 16: 4001b 4000d
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set 17: 4000d D 4002b
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set 18: 4000d D 40028
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set 19: 4001e 4000d
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set 20: 4001e 40028
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set 21: 4002b D 4002a
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set 22: 4000d 4002a
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set 23: 4002b D 4002c D
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set 24: 4002b D 4002c D
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set 25: 4002c D 4002b D
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set 26: 4002b D 4002c D
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set 27: 4002b D 4002c D
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set 28: 4002c D 4002b D
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set 29: 4000c 4002c D
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set 30: 4002c D 4002b D
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set 31: 4002c D 4002b D
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set 32: 4001e D 4002c D
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set 33: 4002c D 4002b D
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set 34: 4001e 4001c D
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set 35: 4001e 4002c D
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set 36: 4001e 4002c D
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set 37: 4001e D 4000b D
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set 38: 4001e D 4002c D
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set 39: 4001e D 4002c D
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set 40: 4002c D 4002b D
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set 41: 4002c D 4002b D
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set 42: 4001e 4002a
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set 43: 40016 D 4001e
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set 44: 40013 D 4002c D
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set 45: 40013 4002c D
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set 46: 4001e D 7b033 D
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set 47: 7b033 4002c D
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set 48: 4001e 4001c
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set 49: 4001e 4002c D
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set 50: 4001b D 4001e
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set 51: 4001b D 4002c D
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set 52: 4001b D 4001e
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set 53: 4002c D 4001d D
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||||
set 54: 4001b 7b033 D
|
||||
set 55: 4002c D 4002b D
|
||||
set 56: 4001b D 4002b
|
||||
set 57: 7b033 D 4002c D
|
||||
set 58: 4002c D 4002b D
|
||||
set 59: 7b033 D 4002c D
|
||||
set 60: 4002c D 4002b D
|
||||
set 61: 7b033 D 4002c D
|
||||
set 62: 4002c D 40029 D
|
||||
set 63: 4002c D 4001d
|
||||
===== Victim Cache contents =====
|
||||
set 0: 10004ee D 1000ad4 D 1000b04 D 1000ac3 D 1000774 1000b02 D 1000ac1 D 1000b38 D 1000ac0 D 1000a13 1000aff D 1000afe D 1000b25 1000a7d 1000abc 1000750
|
||||
===== L2 contents =====
|
||||
set 0: 4002d 4002c 4002a D 4002b D
|
||||
set 1: 4002d 4002a D 4002c 4002b
|
||||
set 2: 4002d 4002c 4002a D 4001d D
|
||||
set 3: 4002d 4002a D 4002c 4002b
|
||||
set 4: 4002d 4002c 4002b D 4001d D
|
||||
set 5: 4002b D 4002a D 4002c 4001d D
|
||||
set 6: 4001d D 4002c 4002a D 4002b
|
||||
set 7: 4002a D 4002c 4002b D 4001d D
|
||||
set 8: 4002b D 4002c 4002a D 40028
|
||||
set 9: 4002c 4002a D 4001d D 40011 D
|
||||
set 10: 4002c 4002b D 40002 40028
|
||||
set 11: 4002a 4002c D 4001d D 40028
|
||||
set 12: 4002b D 4002c 40028 4002a D
|
||||
set 13: 4002c D 4002b 4002a D 40028
|
||||
set 14: 4002c D 4002a D 40028 40013 D
|
||||
set 15: 4002c D 4001d 4002a D 40028
|
||||
set 16: 4001d 4002c D 40028 4002a D
|
||||
set 17: 4002b D 4002c D 40028 4000d D
|
||||
set 18: 4002b D 4002c D 40028 4002a D
|
||||
set 19: 40028 4002b D 4002c D 4000d
|
||||
set 20: 40028 4002c D 4002b D 4001d D
|
||||
set 21: 4002c D 4002a D 4001d D 4002b
|
||||
set 22: 4002b D 4002a 4002c D 4000d D
|
||||
set 23: 4002a D 4002c 4001d D 4002b
|
||||
set 24: 4001d D 4002c 4002a D 4002b
|
||||
set 25: 4002a D 4002c 4001d D 4002b
|
||||
set 26: 4001d D 4002c 4002a D 4002b
|
||||
set 27: 4001d D 4002b D 4002c 4002a D
|
||||
set 28: 4002a D 4002c 4001d D 4002b
|
||||
set 29: 4002c 4002b D 4001d D 4002a D
|
||||
set 30: 4002a D 4002c 4001d D 4002b
|
||||
set 31: 4002a D 4002c 4001d D 4002b
|
||||
set 32: 4002b D 4002c 4001e D 4002a D
|
||||
set 33: 4002a D 4002c 4001d D 4002b
|
||||
set 34: 4002c D 4002b D 4001d D 4001c D
|
||||
set 35: 4002b D 4002c 4002a D 4001d D
|
||||
set 36: 4002b D 4002c 4002a D 4001d D
|
||||
set 37: 4002c D 4002b D 4001c 4001e D
|
||||
set 38: 4002c 4002b D 4002a D 4001d D
|
||||
set 39: 4002b D 4002c 4001c D 4002a D
|
||||
set 40: 4002c 4001c D 4002a D 4002b
|
||||
set 41: 4002a D 4002c 4001d D 4002b
|
||||
set 42: 4002c D 4002a D 4002b D 4001d
|
||||
set 43: 4002c D 4002a 4002b D 4001d D
|
||||
set 44: 4002b D 4002c 40013 D 4002a D
|
||||
set 45: 4002b D 4002c 4001c D 40013
|
||||
set 46: 4002c D 4002b D 40013 D 4002a D
|
||||
set 47: 4002b D 4002c 4001c D 7b033 D
|
||||
set 48: 4002c D 4002b D 4001c 4002a D
|
||||
set 49: 4001c D 4002c 4002b D 4001d D
|
||||
set 50: 4002c D 4002b D 4001d D 4002a D
|
||||
set 51: 4002b D 4002c 4001d D 4002a D
|
||||
set 52: 4001d D 4002c D 4002b D 4001c D
|
||||
set 53: 4002b D 4002c 4002a D 4001c D
|
||||
set 54: 4002c D 4002b D 4001d D 4002a D
|
||||
set 55: 4001c D 4002c 4001d D 4002b
|
||||
set 56: 4002b D 4002c 4001d D 4001b D
|
||||
set 57: 4002c 4002b D 4002a D 4001c D
|
||||
set 58: 4001d D 4002c 4002a D 4002b
|
||||
set 59: 4002c 4002b D 4002a D 4001d D
|
||||
set 60: 4002c 4002a D 4002b 4001d D
|
||||
set 61: 4002c 4002b D 40029 D 4001d D
|
||||
set 62: 4002c 4002a D 4002b 4001d D
|
||||
set 63: 4002c 4001c D 4002b 4002a D
|
||||
====== Simulation results (raw) ======
|
||||
a. number of L1 reads: 70107
|
||||
b. number of L1 read misses: 1927
|
||||
c. number of L1 writes: 29893
|
||||
d. number of L1 write misses: 569
|
||||
e. L1 miss rate: 0.0250
|
||||
f. number of swaps: 1382
|
||||
g. number of victim cache writeback: 766
|
||||
h. number of L2 reads: 2496
|
||||
i. number of L2 read misses: 1268
|
||||
j. number of L2 writes: 766
|
||||
k. number of L2 write misses: 123
|
||||
l. L2 miss rate: 0.5080
|
||||
m. number of L2 writebacks: 415
|
||||
n. total memory traffic: 1806
|
||||
==== Simulation results (performance) ====
|
||||
1. average access time: 0.7874 ns
|
||||
|
|
@ -6,32 +6,40 @@
|
|||
#include <iostream>
|
||||
using namespace std;
|
||||
|
||||
int CacheConfig::getBlockSize() { return blockSize; }
|
||||
int CacheConfig::Size() { return s; }
|
||||
int CacheConfig::Assoc() { return assoc; }
|
||||
int CacheConfig::ReplicementPolicy() { return replicementPolicy; }
|
||||
int CacheConfig::WritePolicy() { return writePolicy; }
|
||||
|
||||
CacheConfig::CacheConfig() {}
|
||||
CacheConfig::CacheConfig(int blockSize, int size, int ass, int vis, int rep, int wrp, string l)
|
||||
CacheConfig::CacheConfig(int blockSize, int size, int assoc, int victimSize, int replicementPolicy, int writePolicy, string level)
|
||||
{
|
||||
this->level = l;
|
||||
this->level = level;
|
||||
this->blockSize = blockSize;
|
||||
this->s = size;
|
||||
this->assoc = ass;
|
||||
this->victimSize = vis;
|
||||
this->replicementPolicy = rep;
|
||||
this->writePolicy = wrp;
|
||||
setupTIO();
|
||||
this->size = size;
|
||||
this->assoc = assoc;
|
||||
this->victimSize = victimSize;
|
||||
this->replicementPolicy = replicementPolicy;
|
||||
this->writePolicy = writePolicy;
|
||||
this->offset = log2(blockSize);
|
||||
index = log2(size / (blockSize * assoc));
|
||||
tag = 32 - this->offset - index;
|
||||
|
||||
offsetMask = (1 << this->offset) - 1;
|
||||
indexMask = ((1 << index) - 1) << this->offset;
|
||||
|
||||
if (!victimSize)
|
||||
return;
|
||||
|
||||
victimOffset = log2(blockSize);
|
||||
victimIndex = 0;
|
||||
victimTag = 32 - victimOffset - victimIndex;
|
||||
victimAssoc = victimSize / blockSize;
|
||||
|
||||
victimOffsetMask = (1 << victimOffset) - 1;
|
||||
}
|
||||
double CacheConfig::getHT()
|
||||
{
|
||||
return 0.25 + 2.5 * (s / (512.0 * 1024)) + 0.025 * (blockSize / 16.0) + 0.025 * assoc;
|
||||
return 0.25 + 2.5 * (size / (512.0 * 1024)) + 0.025 * (blockSize / 16.0) + 0.025 * assoc;
|
||||
}
|
||||
|
||||
double CacheConfig::getHT2()
|
||||
{
|
||||
return 2.5 + 2.5 * (s / (512.0 * 1024)) + 0.025 * (blockSize / 16.0) + 0.025 * assoc;
|
||||
return 2.5 + 2.5 * (size / (512.0 * 1024)) + 0.025 * (blockSize / 16.0) + 0.025 * assoc;
|
||||
}
|
||||
|
||||
double CacheConfig::getMP()
|
||||
|
|
@ -49,74 +57,41 @@ uint32_t CacheConfig::getMaxIndex()
|
|||
return (1 << index);
|
||||
}
|
||||
|
||||
uint32_t CacheConfig::getVictimAs()
|
||||
{
|
||||
return victimAsso;
|
||||
}
|
||||
|
||||
uint32_t CacheConfig::getAs()
|
||||
{
|
||||
return assoc;
|
||||
}
|
||||
|
||||
void CacheConfig::setupTIO()
|
||||
{
|
||||
// setup tag, index, b
|
||||
o = log2(blockSize);
|
||||
index = log2(s / (blockSize * assoc));
|
||||
tag = 32 - o - index;
|
||||
|
||||
offsetMask = (1 << o) - 1;
|
||||
indexMask = ((1 << index) - 1) << o;
|
||||
|
||||
if (!victimSize)
|
||||
return;
|
||||
|
||||
victimOffset = log2(blockSize);
|
||||
victimIndex = 0;
|
||||
victimTag = 32 - victimOffset - victimIndex;
|
||||
victimAsso = victimSize / blockSize;
|
||||
|
||||
vom = (1 << victimOffset) - 1;
|
||||
// vim = ((1<<victimIndex)-1) << victimOffset;
|
||||
}
|
||||
|
||||
CacheIndex CacheConfig::parserVictimAddr(uint32_t addr)
|
||||
{
|
||||
uint32_t offset = addr & vom;
|
||||
// uint32_t index = (addr & vim) >> victimOffset;
|
||||
uint32_t offset = addr & victimOffsetMask;
|
||||
uint32_t tag = addr >> victimOffset;
|
||||
return {tag, 0, offset, addr};
|
||||
}
|
||||
|
||||
CacheIndex CacheConfig::AddrParser(uint32_t addr)
|
||||
CacheIndex CacheConfig::addrParser(uint32_t addr)
|
||||
{
|
||||
uint32_t offset = addr & offsetMask;
|
||||
uint32_t index = (addr & indexMask) >> o;
|
||||
uint32_t tag = addr >> (o + this->index);
|
||||
uint32_t index = (addr & indexMask) >> this->offset;
|
||||
uint32_t tag = addr >> (this->offset + this->index);
|
||||
return {tag, index, offset, addr};
|
||||
}
|
||||
|
||||
uint32_t CacheConfig::UnParser(uint32_t tag, CacheIndex tio)
|
||||
uint32_t CacheConfig::reparserAddr(uint32_t tag, CacheIndex tio)
|
||||
{
|
||||
return (tag << (o + index)) | (tio.index << o) | (tio.offset);
|
||||
return (tag << (this->offset + index)) | (tio.index << this->offset) | (tio.offset);
|
||||
}
|
||||
|
||||
uint32_t CacheConfig::UnParserVic(uint32_t tag, CacheIndex tio)
|
||||
uint32_t CacheConfig::reparserVictimAddr(uint32_t tag, CacheIndex tio)
|
||||
{
|
||||
return (tag << (victimOffset)) | (tio.offset);
|
||||
}
|
||||
|
||||
Cache::Cache(CacheConfig* config, Cache* nextCache)
|
||||
Cache::Cache(CacheConfig *config, Cache *nextCache)
|
||||
{
|
||||
|
||||
this->config = config;
|
||||
cache.resize(config->getMaxIndex());
|
||||
for (auto &b : cache)
|
||||
b.resize(config->getAs());
|
||||
b.resize(config->assoc);
|
||||
|
||||
if (config->victimSize)
|
||||
victimCache.resize(config->getVictimAs());
|
||||
victimCache.resize(config->victimAssoc);
|
||||
|
||||
this->nextCache = nextCache;
|
||||
}
|
||||
|
|
@ -126,20 +101,20 @@ void Cache::useCache(uint32_t rawAddr, bool isWrite)
|
|||
|
||||
isWrite ? writeCount++ : readCount++;
|
||||
|
||||
auto addr = config->AddrParser(rawAddr);
|
||||
auto s = &cache[addr.index];
|
||||
auto addr = config->addrParser(rawAddr);
|
||||
auto set = &cache[addr.index];
|
||||
|
||||
auto cl = find_if(
|
||||
s->begin(),
|
||||
s->end(),
|
||||
set->begin(),
|
||||
set->end(),
|
||||
[=](const Block &b)
|
||||
{
|
||||
return b.valid && b.tag == addr.tag;
|
||||
});
|
||||
|
||||
if (cl != s->end())
|
||||
if (cl != set->end())
|
||||
{
|
||||
for (auto &b : (*s))
|
||||
for (auto &b : (*set))
|
||||
b.lru += (b.lru < cl->lru);
|
||||
cl->lru = 0;
|
||||
cl->dirty |= isWrite;
|
||||
|
|
@ -148,19 +123,19 @@ void Cache::useCache(uint32_t rawAddr, bool isWrite)
|
|||
|
||||
// Main Cache Miss
|
||||
cl = find_if(
|
||||
s->begin(),
|
||||
s->end(),
|
||||
set->begin(),
|
||||
set->end(),
|
||||
[](const Block &b)
|
||||
{
|
||||
return !b.valid;
|
||||
});
|
||||
|
||||
if (cl == s->end())
|
||||
if (cl == set->end())
|
||||
{
|
||||
// Replace
|
||||
cl = max_element(
|
||||
s->begin(),
|
||||
s->end());
|
||||
set->begin(),
|
||||
set->end());
|
||||
}
|
||||
|
||||
if (!victimCache.size())
|
||||
|
|
@ -174,7 +149,7 @@ void Cache::useCache(uint32_t rawAddr, bool isWrite)
|
|||
writeBack++;
|
||||
if (nextCache != nullptr)
|
||||
{
|
||||
nextCache->useCache(config->UnParser(cl->tag, addr), true);
|
||||
nextCache->useCache(config->reparserAddr(cl->tag, addr), true);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -184,7 +159,7 @@ void Cache::useCache(uint32_t rawAddr, bool isWrite)
|
|||
nextCache->useCache(rawAddr, false);
|
||||
}
|
||||
|
||||
for (auto &b : (*s))
|
||||
for (auto &b : (*set))
|
||||
b.lru++;
|
||||
*cl = {addr.tag, 0, isWrite, true};
|
||||
}
|
||||
|
|
@ -209,10 +184,10 @@ void Cache::useCache(uint32_t rawAddr, bool isWrite)
|
|||
{
|
||||
for (auto &b : *vcp)
|
||||
b.lru += (b.lru < tmp.lru);
|
||||
*vic = {config->parserVictimAddr(config->UnParser(cl->tag, addr)).tag, 0, cl->dirty, true};
|
||||
*vic = {config->parserVictimAddr(config->reparserAddr(cl->tag, addr)).tag, 0, cl->dirty, true};
|
||||
}
|
||||
|
||||
for (auto &b : (*s))
|
||||
for (auto &b : (*set))
|
||||
b.lru++;
|
||||
*cl = {addr.tag, 0, isWrite || tmp.dirty, true};
|
||||
exchange++;
|
||||
|
|
@ -227,7 +202,7 @@ void Cache::useCache(uint32_t rawAddr, bool isWrite)
|
|||
{
|
||||
nextCache->useCache(rawAddr, false);
|
||||
}
|
||||
for (auto &b : (*s))
|
||||
for (auto &b : (*set))
|
||||
b.lru++;
|
||||
*cl = {addr.tag, 0, isWrite, true};
|
||||
return;
|
||||
|
|
@ -251,15 +226,15 @@ void Cache::useCache(uint32_t rawAddr, bool isWrite)
|
|||
writeBack++;
|
||||
if (nextCache != nullptr)
|
||||
{
|
||||
nextCache->useCache(config->UnParserVic(vic->tag, vaddr), true);
|
||||
nextCache->useCache(config->reparserVictimAddr(vic->tag, vaddr), true);
|
||||
}
|
||||
}
|
||||
}
|
||||
for (auto &b : *vcp)
|
||||
b.lru++;
|
||||
*vic = {config->parserVictimAddr(config->UnParser(cl->tag, addr)).tag, 0, cl->dirty, true};
|
||||
*vic = {config->parserVictimAddr(config->reparserAddr(cl->tag, addr)).tag, 0, cl->dirty, true};
|
||||
|
||||
for (auto &b : (*s))
|
||||
for (auto &b : (*set))
|
||||
b.lru++;
|
||||
*cl = {addr.tag, 0, isWrite, true};
|
||||
if (nextCache != nullptr)
|
||||
|
|
@ -273,7 +248,7 @@ void Cache::useCache(uint32_t rawAddr, bool isWrite)
|
|||
|
||||
void Cache::printCache()
|
||||
{
|
||||
if (!this->config->Size())
|
||||
if (!this->config->size)
|
||||
return;
|
||||
cout << "===== " << this->config->level << " contents =====" << endl;
|
||||
for (unsigned i = 0; i != this->cache.size(); i++)
|
||||
|
|
@ -317,4 +292,7 @@ double Cache::getAAT()
|
|||
return HT + (MP * MR);
|
||||
}
|
||||
|
||||
int Cache::getCommunication() { return readMiss + writeMiss + writeBack; }
|
||||
int Cache::getCommunication()
|
||||
{
|
||||
return readMiss + writeMiss + writeBack;
|
||||
}
|
||||
|
|
@ -19,17 +19,17 @@ public:
|
|||
string level;
|
||||
|
||||
int blockSize;
|
||||
int s; // Size
|
||||
int assoc; // Assoc
|
||||
int size;
|
||||
int assoc;
|
||||
int replicementPolicy;
|
||||
int writePolicy;
|
||||
|
||||
int victimSize;
|
||||
int victimAsso;
|
||||
int victimAssoc;
|
||||
|
||||
int tag; // tag bit
|
||||
int index; // index
|
||||
int o; // offset
|
||||
int tag;
|
||||
int index;
|
||||
int offset;
|
||||
|
||||
uint32_t offsetMask;
|
||||
uint32_t indexMask;
|
||||
|
|
@ -38,29 +38,22 @@ public:
|
|||
int victimIndex;
|
||||
int victimOffset;
|
||||
|
||||
uint32_t vom; // victim offset mask
|
||||
uint32_t vim; // victim index mask
|
||||
|
||||
CacheConfig();
|
||||
CacheConfig(int blockSize, int size, int ass, int vis, int rep, int wrp, string l);
|
||||
uint32_t victimOffsetMask;
|
||||
uint32_t victimIndexMask;
|
||||
|
||||
CacheConfig(int blockSize, int size, int assoc, int victimSize, int replicementPolicy, int writePolicy, string level);
|
||||
|
||||
double getHT();
|
||||
double getHT2();
|
||||
double getMP();
|
||||
int log2(uint32_t x);
|
||||
uint32_t getMaxIndex();
|
||||
uint32_t getVictimAs();
|
||||
uint32_t getAs();
|
||||
void setupTIO();
|
||||
|
||||
CacheIndex parserVictimAddr(uint32_t addr);
|
||||
CacheIndex AddrParser(uint32_t addr);
|
||||
uint32_t UnParser(uint32_t tag, CacheIndex tio);
|
||||
uint32_t UnParserVic(uint32_t tag, CacheIndex tio);
|
||||
int getBlockSize();
|
||||
int Size();
|
||||
int Assoc();
|
||||
int ReplicementPolicy();
|
||||
int WritePolicy();
|
||||
CacheIndex addrParser(uint32_t addr);
|
||||
uint32_t reparserAddr(uint32_t tag, CacheIndex tio);
|
||||
uint32_t reparserVictimAddr(uint32_t tag, CacheIndex tio);
|
||||
|
||||
};
|
||||
|
||||
struct Block
|
||||
|
|
|
|||
Binary file not shown.
Binary file not shown.
Loading…
Reference in New Issue