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fix 6

This commit is contained in:
LYC 2024-10-31 10:56:07 +08:00
parent c03fafcf95
commit 52ac2e49dc
9 changed files with 74 additions and 560 deletions
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60
cache/Project1/Proj1-2/Proj1-2/output/test1.txt vendored
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===== Simulator configuration =====
BLOCKSIZE: 32
L1_SIZE: 2048
L1_ASSOC: 4
Victim_Cache_SIZE: 0
L2_SIZE: 4096
L2_ASSOC: 8
trace_file: gcc_trace.txt
===================================
===== L1 contents =====
set 0: 20028d D 20018a 20028e D 200198 D
set 1: 2001c1 D 20028d D 200153 D 20013b
set 2: 200223 D 20028d D 200241 2001c1
set 3: 20018a 2001ac D 20028e D 20028d D
set 4: 20018f D 2000f9 20017a D 20018a
set 5: 200009 20017a 2000fa 20018a
set 6: 200009 2000f9 20028d D 20018a
set 7: 200009 2001ac 2000fa 200149
set 8: 200009 3d819c D 20017b D 2000f9
set 9: 200009 2000fa 2000f9 2001b2 D
set 10: 200009 200214 2000fa 20023f
set 11: 200009 2001ab 20013a 20023f
set 12: 20018f D 2001f2 2001aa 20018a D
set 13: 20028d D 20018d D 20013a 20028c D
set 14: 20013a 20018d D 20028d D 2001ad D
set 15: 2001f8 D 20028c D 20013a 20018d D
===== L2 contents =====
set 0: 20018a 20028e 200198 2001ab 2001d1 D 20017a D 20028d 2001f4 D
set 1: 2001c1 200153 D 20028e D 20013b 200198 D 2000fb 2001d1 D 20028d
set 2: 200241 20028d D 200223 200149 200198 D 20018a 2001c1 D 20013b
set 3: 2001ac 2001c1 D 20028e 2001b0 D 20028d 20028c D 20018a 2001bd D
set 4: 2000f9 20028e D 20018a 20028d D 20017a D 20023f 200149 2002b1 D
set 5: 20017a 20028e D 200009 20028d D 2000fa 2001b2 D 20018a 20023f
set 6: 200009 2000f9 2001b2 D 20023f 2001ac D 2001ad D 20028d 20028c D
set 7: 200009 20028d D 2000fa 2001b2 D 2001ac 20023f 200149 2001f6 D
set 8: 200009 20017b D 2000fa 2001b2 D 2000f9 20028d D 20023f 200149
set 9: 200009 2000fa 20028d D 2001b2 20023f 3d819c D 20028c D 2001aa
set 10: 200009 200214 D 20028d D 20023f 2001ab D 2001aa 2001fc D 2000fa
set 11: 200009 2001ab 20028d D 20023f 2001aa 200214 D 20028c D 20013a
set 12: 20018f 2001aa 20018a 2001f2 20023f 20028d D 20018d D 2001ab
set 13: 20028d 2001b3 D 20018d 2001ab D 20013a 2001b2 D 20028c 2001fe D
set 14: 20028d 20028c D 20018d 2001a7 D 20013a 2001b2 D 2001ad D 2001fd D
set 15: 20013a 20028d D 20018d 200197 D 2001f8 2001a9 D 200222 D 2001d1 D
====== Simulation results (raw) ======
a. number of L1 reads: 63640
b. number of L1 read misses: 5170
c. number of L1 writes: 36360
d. number of L1 write misses: 4452
e. L1 miss rate: 0.0962
f. number of swaps: 0
g. number of victim cache writeback: 0
h. number of L2 reads: 9622
i. number of L2 read misses: 5313
j. number of L2 writes: 4942
k. number of L2 write misses: 151
l. L2 miss rate: 0.5522
m. number of L2 writebacks: 2978
n. total memory traffic: 8442
==== Simulation results (performance) ====
1. average access time: 1.7920 ns

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===== Simulator configuration =====
BLOCKSIZE: 16
L1_SIZE: 1024
L1_ASSOC: 8
Victim_Cache_SIZE: 0
L2_SIZE: 8192
L2_ASSOC: 4
trace_file: go_trace.txt
===================================
===== L1 contents =====
set 0: 800470 D 80046f D 80046e D 80046d D 80046c D 80046b D 80046a D 800469 D
set 1: 800470 D 80046f D 80046e D 80046d D 80046c D 80046b D 80046a D 800469 D
set 2: 800470 D 80046f D 80046e D 80046d D 80046c D 80046b D 80046a D 800469 D
set 3: 800470 D 80046f D 80046e D 80046d D 80046c D 80046b D 80046a D 800469 D
set 4: 800470 D 80046f D 80046e D 80046d D 80046c D 80046b D 80046a D 800469 D
set 5: 80046f D 80046e D 80046d D 80046c D 80046b D 80046a D 800469 D 800468 D
set 6: 80046f D 80046e D 80046d D 80046c D 80046b D 80046a D 800469 D 800468 D
set 7: 80046f D 80046e D 80046d D 80046c D 80046b D 80046a D 800469 D 800468 D
===== L2 contents =====
set 0: 80047 80046 D 80045 D 80044 D
set 1: 80047 80046 D 80045 D 80044 D
set 2: 80047 80046 D 80045 D 80044 D
set 3: 80047 80046 D 80045 D 80044 D
set 4: 80047 80046 D 80045 D 80044 D
set 5: 80046 D 80045 D 80044 D 80043 D
set 6: 80046 D 80045 D 80044 D 80043 D
set 7: 80046 D 80045 D 80044 D 80043 D
set 8: 80046 D 80045 D 80044 D 80043 D
set 9: 80046 D 80045 D 80044 D 80043 D
set 10: 80046 D 80045 D 80044 D 80043 D
set 11: 80046 D 80045 D 80044 D 80043 D
set 12: 80046 D 80045 D 80044 D 80043 D
set 13: 80046 D 80045 D 80044 D 80043 D
set 14: 80046 D 80045 D 80044 D 80043 D
set 15: 80046 D 80045 D 80044 D 80043 D
set 16: 80046 D 80045 D 80044 D 80043 D
set 17: 80046 D 80045 D 80044 D 80043 D
set 18: 80046 D 80045 D 80044 D 80043 D
set 19: 80046 D 80045 D 80044 D 80043 D
set 20: 80046 D 80045 D 80044 D 80043 D
set 21: 80046 D 80045 D 80044 D 80043 D
set 22: 80046 D 80045 D 80044 D 80043 D
set 23: 80046 D 80045 D 80044 D 80043 D
set 24: 80046 D 80045 D 80044 D 80043 D
set 25: 80046 D 80045 D 80044 D 80043 D
set 26: 80046 D 80045 D 80044 D 80043 D
set 27: 80046 D 80045 D 80044 D 80043 D
set 28: 80046 D 80045 D 80044 D 80043 D
set 29: 80046 D 80045 D 80044 D 80043 D
set 30: 80046 D 80045 D 80044 D 80043 D
set 31: 80046 D 80045 D 80044 D 80043 D
set 32: 80046 D 80045 D 80044 D 80043 D
set 33: 80046 D 80045 D 80044 D 80043 D
set 34: 80046 D 80045 D 80044 D 80043 D
set 35: 80046 D 80045 D 80044 D 80043 D
set 36: 80046 D 80045 D 80044 D 80043 D
set 37: 80046 D 80045 D 80044 D 80043 D
set 38: 80046 D 80045 D 80044 D 80043 D
set 39: 80046 D 80045 D 80044 D 80043 D
set 40: 80046 D 80045 D 80044 D 80043 D
set 41: 80046 D 80045 D 80044 D 80043 D
set 42: 80046 D 80045 D 80044 D 80043 D
set 43: 80046 D 80045 D 80044 D 80043 D
set 44: 80046 D 80045 D 80044 D 80043 D
set 45: 80046 D 80045 D 80044 D 80043 D
set 46: 80046 D 80045 D 80044 D 80043 D
set 47: 80046 D 80045 D 80044 D 80043 D
set 48: 80046 D 80045 D 80044 D 80043 D
set 49: 80046 D 80045 D 80044 D 80043 D
set 50: 80046 D 80045 D 80044 D 80043 D
set 51: 80046 D 80045 D 80044 D 80043 D
set 52: 80046 D 80045 D 80044 D 80043 D
set 53: 80046 D 80045 D 80044 D 80043 D
set 54: 80046 D 80045 D 80044 D 80043 D
set 55: 80046 D 80045 D 80044 D 80043 D
set 56: 80046 D 80045 D 80044 D 80043 D
set 57: 80046 D 80045 D 80044 D 80043 D
set 58: 80046 D 80045 D 80044 D 80043 D
set 59: 80046 D 80045 D 80044 D 80043 D
set 60: 80046 D 80045 D 80044 D 80043 D
set 61: 80046 D 80045 D 80044 D 80043 D
set 62: 80046 D 80045 D 80044 D 80043 D
set 63: 80046 D 80045 D 80044 D 80043 D
set 64: 80046 D 80045 D 80044 D 80043 D
set 65: 80046 D 80045 D 80044 D 80043 D
set 66: 80046 D 80045 D 80044 D 80043 D
set 67: 80046 D 80045 D 80044 D 80043 D
set 68: 80046 D 80045 D 80044 D 80043 D
set 69: 80046 80045 D 80044 D 80043 D
set 70: 80046 80045 D 80044 D 80043 D
set 71: 80046 80045 D 80044 D 80043 D
set 72: 80046 80045 D 80044 D 80043 D
set 73: 80046 80045 D 80044 D 80043 D
set 74: 80046 80045 D 80044 D 80043 D
set 75: 80046 80045 D 80044 D 80043 D
set 76: 80046 80045 D 80044 D 80043 D
set 77: 80046 80045 D 80044 D 80043 D
set 78: 80046 80045 D 80044 D 80043 D
set 79: 80046 80045 D 80044 D 80043 D
set 80: 80046 80045 D 80044 D 80043 D
set 81: 80046 80045 D 80044 D 80043 D
set 82: 80046 80045 D 80044 D 80043 D
set 83: 80046 80045 D 80044 D 80043 D
set 84: 80046 80045 D 80044 D 80043 D
set 85: 80046 80045 D 80044 D 80043 D
set 86: 80046 80045 D 80044 D 80043 D
set 87: 80046 80045 D 80044 D 80043 D
set 88: 80046 80045 D 80044 D 80043 D
set 89: 80046 80045 D 80044 D 80043 D
set 90: 80046 80045 D 80044 D 80043 D
set 91: 80046 80045 D 80044 D 80043 D
set 92: 80046 80045 D 80044 D 80043 D
set 93: 80046 80045 D 80044 D 80043 D
set 94: 80046 80045 D 80044 D 80043 D
set 95: 80046 80045 D 80044 D 80043 D
set 96: 80046 80045 D 80044 D 80043 D
set 97: 80046 80045 D 80044 D 80043 D
set 98: 80046 80045 D 80044 D 80043 D
set 99: 80046 80045 D 80044 D 80043 D
set 100: 80046 80045 D 80044 D 80043 D
set 101: 80046 80045 D 80044 D 80043 D
set 102: 80046 80045 D 80044 D 80043 D
set 103: 80046 80045 D 80044 D 80043 D
set 104: 80046 80045 D 80044 D 80043 D
set 105: 80046 80045 D 80044 D 80043 D
set 106: 80046 80045 D 80044 D 80043 D
set 107: 80046 80045 D 80044 D 80043 D
set 108: 80046 80045 D 80044 D 80043 D
set 109: 80046 80045 D 80044 D 80043 D
set 110: 80046 80045 D 80044 D 80043 D
set 111: 80046 80045 D 80044 D 80043 D
set 112: 80046 80045 D 80044 D 80043 D
set 113: 80046 80045 D 80044 D 80043 D
set 114: 80046 80045 D 80044 D 80043 D
set 115: 80046 80045 D 80044 D 80043 D
set 116: 80046 80045 D 80044 D 80043 D
set 117: 80046 80045 D 80044 D 80043 D
set 118: 80046 80045 D 80044 D 80043 D
set 119: 80046 80045 D 80044 D 80043 D
set 120: 80046 80045 D 80044 D 80043 D
set 121: 80046 80045 D 80044 D 80043 D
set 122: 80046 80045 D 80044 D 80043 D
set 123: 80046 80045 D 80044 D 80043 D
set 124: 80046 80045 D 80044 D 80043 D
set 125: 80046 80045 D 80044 D 80043 D
set 126: 80046 80045 D 80044 D 80043 D
set 127: 80046 80045 D 80044 D 80043 D
====== Simulation results (raw) ======
a. number of L1 reads: 60613
b. number of L1 read misses: 3819
c. number of L1 writes: 39387
d. number of L1 write misses: 6341
e. L1 miss rate: 0.1016
f. number of swaps: 0
g. number of victim cache writeback: 0
h. number of L2 reads: 10160
i. number of L2 read misses: 9847
j. number of L2 writes: 8323
k. number of L2 write misses: 3
l. L2 miss rate: 0.9692
m. number of L2 writebacks: 7869
n. total memory traffic: 17719
==== Simulation results (performance) ====
1. average access time: 2.7692 ns

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===== Simulator configuration =====
BLOCKSIZE: 32
L1_SIZE: 1024
L1_ASSOC: 8
Victim_Cache_SIZE: 256
L2_SIZE: 0
L2_ASSOC: 0
trace_file: perl_trace.txt
===================================
===== L1 contents =====
set 0: 8003d7 80037c D 800276 D 8003d8 800379 800368 f6067b D 8003d9
set 1: 80056c 800045 80058c 8003d7 8002c1 D 800379 8003d8 80037b
set 2: 800045 80058c D 8003d2 800379 D f6067d D 80018e 8003d8 f60677
set 3: 800580 8003d1 f6067d D 800325 80018e 8003d8 8003d2 D 800276
===== Victim Cache contents =====
set 0: 2000f4f 3d819ed D 20006a2 D 20009da 3d819dd 20006a1 20006a5 D 2000f4c D
====== Simulation results (raw) ======
a. number of L1 reads: 70107
b. number of L1 read misses: 14002
c. number of L1 writes: 29893
d. number of L1 write misses: 4835
e. L1 miss rate: 0.1884
f. number of swaps: 4060
g. number of victim cache writeback: 6735
h. number of L2 reads: 0
i. number of L2 read misses: 0
j. number of L2 writes: 0
k. number of L2 write misses: 0
l. L2 miss rate: 0
m. number of L2 writebacks: 0
n. total memory traffic: 25572
==== Simulation results (performance) ====
1. average access time: 4.4607 ns

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===== Simulator configuration =====
BLOCKSIZE: 128
L1_SIZE: 1024
L1_ASSOC: 2
Victim_Cache_SIZE: 1024
L2_SIZE: 4096
L2_ASSOC: 4
trace_file: gcc_trace.txt
===================================
===== L1 contents =====
set 0: 2001c1 D 20028d D
set 1: 200009 20017a
set 2: 200009 200214
set 3: 2001f8 D 20028c D
===== Victim Cache contents =====
set 0: f60672 D 80063d D 80088c D 800904 8006b1 800628 8006ae 80063f D
===== L2 contents =====
set 0: 1000c5 1000d6 D 100147 D 1000cc D
set 1: 1000bd D 100147 D 10007d 1000d6
set 2: 10010a 1000d9 D 10009d 10007d
set 3: 1000fc D 1000c5 D 1000d5 10009d
set 4: 1000a9 D 100120 100111 100146 D
set 5: 100004 10007c 1000c7 D 100146 D
set 6: 100004 1000bd D 1000d5 10007c
set 7: 1000c7 1000d5 1000c6 D 10011f
====== Simulation results (raw) ======
a. number of L1 reads: 63640
b. number of L1 read misses: 8160
c. number of L1 writes: 36360
d. number of L1 write misses: 3824
e. L1 miss rate: 0.1198
f. number of swaps: 9722
g. number of victim cache writeback: 4763
h. number of L2 reads: 11984
i. number of L2 read misses: 7690
j. number of L2 writes: 4763
k. number of L2 write misses: 1205
l. L2 miss rate: 0.6417
m. number of L2 writebacks: 3198
n. total memory traffic: 12093
==== Simulation results (performance) ====
1. average access time: 2.6884 ns

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===== Simulator configuration =====
BLOCKSIZE: 64
L1_SIZE: 8192
L1_ASSOC: 2
Victim_Cache_SIZE: 1024
L2_SIZE: 16384
L2_ASSOC: 4
trace_file: perl_trace.txt
===================================
===== L1 contents =====
set 0: 4002d D 4002c D
set 1: 4002c D 4002d D
set 2: 40016 D 4002d D
set 3: 4002d D 4002c D
set 4: 4002d D 4001d D
set 5: 4002a 4002c D
set 6: 4002b D 4002c D
set 7: 4001d 4002c D
set 8: 4000f D 4002c D
set 9: 40011 D 4002c D
set 10: 40002 4002c D
set 11: 40002 40019
set 12: 4002c D 40028
set 13: 40013 D 4002b
set 14: 40013 D 4002c
set 15: 4001d 40028
set 16: 4001b 4000d
set 17: 4000d D 4002b
set 18: 4000d D 40028
set 19: 4001e 4000d
set 20: 4001e 40028
set 21: 4002b D 4002a
set 22: 4000d 4002a
set 23: 4002b D 4002c D
set 24: 4002b D 4002c D
set 25: 4002c D 4002b D
set 26: 4002b D 4002c D
set 27: 4002b D 4002c D
set 28: 4002c D 4002b D
set 29: 4000c 4002c D
set 30: 4002c D 4002b D
set 31: 4002c D 4002b D
set 32: 4001e D 4002c D
set 33: 4002c D 4002b D
set 34: 4001e 4001c D
set 35: 4001e 4002c D
set 36: 4001e 4002c D
set 37: 4001e D 4000b D
set 38: 4001e D 4002c D
set 39: 4001e D 4002c D
set 40: 4002c D 4002b D
set 41: 4002c D 4002b D
set 42: 4001e 4002a
set 43: 40016 D 4001e
set 44: 40013 D 4002c D
set 45: 40013 4002c D
set 46: 4001e D 7b033 D
set 47: 7b033 4002c D
set 48: 4001e 4001c
set 49: 4001e 4002c D
set 50: 4001b D 4001e
set 51: 4001b D 4002c D
set 52: 4001b D 4001e
set 53: 4002c D 4001d D
set 54: 4001b 7b033 D
set 55: 4002c D 4002b D
set 56: 4001b D 4002b
set 57: 7b033 D 4002c D
set 58: 4002c D 4002b D
set 59: 7b033 D 4002c D
set 60: 4002c D 4002b D
set 61: 7b033 D 4002c D
set 62: 4002c D 40029 D
set 63: 4002c D 4001d
===== Victim Cache contents =====
set 0: 10004ee D 1000ad4 D 1000b04 D 1000ac3 D 1000774 1000b02 D 1000ac1 D 1000b38 D 1000ac0 D 1000a13 1000aff D 1000afe D 1000b25 1000a7d 1000abc 1000750
===== L2 contents =====
set 0: 4002d 4002c 4002a D 4002b D
set 1: 4002d 4002a D 4002c 4002b
set 2: 4002d 4002c 4002a D 4001d D
set 3: 4002d 4002a D 4002c 4002b
set 4: 4002d 4002c 4002b D 4001d D
set 5: 4002b D 4002a D 4002c 4001d D
set 6: 4001d D 4002c 4002a D 4002b
set 7: 4002a D 4002c 4002b D 4001d D
set 8: 4002b D 4002c 4002a D 40028
set 9: 4002c 4002a D 4001d D 40011 D
set 10: 4002c 4002b D 40002 40028
set 11: 4002a 4002c D 4001d D 40028
set 12: 4002b D 4002c 40028 4002a D
set 13: 4002c D 4002b 4002a D 40028
set 14: 4002c D 4002a D 40028 40013 D
set 15: 4002c D 4001d 4002a D 40028
set 16: 4001d 4002c D 40028 4002a D
set 17: 4002b D 4002c D 40028 4000d D
set 18: 4002b D 4002c D 40028 4002a D
set 19: 40028 4002b D 4002c D 4000d
set 20: 40028 4002c D 4002b D 4001d D
set 21: 4002c D 4002a D 4001d D 4002b
set 22: 4002b D 4002a 4002c D 4000d D
set 23: 4002a D 4002c 4001d D 4002b
set 24: 4001d D 4002c 4002a D 4002b
set 25: 4002a D 4002c 4001d D 4002b
set 26: 4001d D 4002c 4002a D 4002b
set 27: 4001d D 4002b D 4002c 4002a D
set 28: 4002a D 4002c 4001d D 4002b
set 29: 4002c 4002b D 4001d D 4002a D
set 30: 4002a D 4002c 4001d D 4002b
set 31: 4002a D 4002c 4001d D 4002b
set 32: 4002b D 4002c 4001e D 4002a D
set 33: 4002a D 4002c 4001d D 4002b
set 34: 4002c D 4002b D 4001d D 4001c D
set 35: 4002b D 4002c 4002a D 4001d D
set 36: 4002b D 4002c 4002a D 4001d D
set 37: 4002c D 4002b D 4001c 4001e D
set 38: 4002c 4002b D 4002a D 4001d D
set 39: 4002b D 4002c 4001c D 4002a D
set 40: 4002c 4001c D 4002a D 4002b
set 41: 4002a D 4002c 4001d D 4002b
set 42: 4002c D 4002a D 4002b D 4001d
set 43: 4002c D 4002a 4002b D 4001d D
set 44: 4002b D 4002c 40013 D 4002a D
set 45: 4002b D 4002c 4001c D 40013
set 46: 4002c D 4002b D 40013 D 4002a D
set 47: 4002b D 4002c 4001c D 7b033 D
set 48: 4002c D 4002b D 4001c 4002a D
set 49: 4001c D 4002c 4002b D 4001d D
set 50: 4002c D 4002b D 4001d D 4002a D
set 51: 4002b D 4002c 4001d D 4002a D
set 52: 4001d D 4002c D 4002b D 4001c D
set 53: 4002b D 4002c 4002a D 4001c D
set 54: 4002c D 4002b D 4001d D 4002a D
set 55: 4001c D 4002c 4001d D 4002b
set 56: 4002b D 4002c 4001d D 4001b D
set 57: 4002c 4002b D 4002a D 4001c D
set 58: 4001d D 4002c 4002a D 4002b
set 59: 4002c 4002b D 4002a D 4001d D
set 60: 4002c 4002a D 4002b 4001d D
set 61: 4002c 4002b D 40029 D 4001d D
set 62: 4002c 4002a D 4002b 4001d D
set 63: 4002c 4001c D 4002b 4002a D
====== Simulation results (raw) ======
a. number of L1 reads: 70107
b. number of L1 read misses: 1927
c. number of L1 writes: 29893
d. number of L1 write misses: 569
e. L1 miss rate: 0.0250
f. number of swaps: 1382
g. number of victim cache writeback: 766
h. number of L2 reads: 2496
i. number of L2 read misses: 1268
j. number of L2 writes: 766
k. number of L2 write misses: 123
l. L2 miss rate: 0.5080
m. number of L2 writebacks: 415
n. total memory traffic: 1806
==== Simulation results (performance) ====
1. average access time: 0.7874 ns

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#include <iostream> #include <iostream>
using namespace std; using namespace std;
int CacheConfig::getBlockSize() { return blockSize; } CacheConfig::CacheConfig(int blockSize, int size, int assoc, int victimSize, int replicementPolicy, int writePolicy, string level)
int CacheConfig::Size() { return s; }
int CacheConfig::Assoc() { return assoc; }
int CacheConfig::ReplicementPolicy() { return replicementPolicy; }
int CacheConfig::WritePolicy() { return writePolicy; }
CacheConfig::CacheConfig() {}
CacheConfig::CacheConfig(int blockSize, int size, int ass, int vis, int rep, int wrp, string l)
{ {
this->level = l; this->level = level;
this->blockSize = blockSize; this->blockSize = blockSize;
this->s = size; this->size = size;
this->assoc = ass; this->assoc = assoc;
this->victimSize = vis; this->victimSize = victimSize;
this->replicementPolicy = rep; this->replicementPolicy = replicementPolicy;
this->writePolicy = wrp; this->writePolicy = writePolicy;
setupTIO(); this->offset = log2(blockSize);
index = log2(size / (blockSize * assoc));
tag = 32 - this->offset - index;
offsetMask = (1 << this->offset) - 1;
indexMask = ((1 << index) - 1) << this->offset;
if (!victimSize)
return;
victimOffset = log2(blockSize);
victimIndex = 0;
victimTag = 32 - victimOffset - victimIndex;
victimAssoc = victimSize / blockSize;
victimOffsetMask = (1 << victimOffset) - 1;
} }
double CacheConfig::getHT() double CacheConfig::getHT()
{ {
return 0.25 + 2.5 * (s / (512.0 * 1024)) + 0.025 * (blockSize / 16.0) + 0.025 * assoc; return 0.25 + 2.5 * (size / (512.0 * 1024)) + 0.025 * (blockSize / 16.0) + 0.025 * assoc;
} }
double CacheConfig::getHT2() double CacheConfig::getHT2()
{ {
return 2.5 + 2.5 * (s / (512.0 * 1024)) + 0.025 * (blockSize / 16.0) + 0.025 * assoc; return 2.5 + 2.5 * (size / (512.0 * 1024)) + 0.025 * (blockSize / 16.0) + 0.025 * assoc;
} }
double CacheConfig::getMP() double CacheConfig::getMP()
@ -49,60 +57,27 @@ uint32_t CacheConfig::getMaxIndex()
return (1 << index); return (1 << index);
} }
uint32_t CacheConfig::getVictimAs()
{
return victimAsso;
}
uint32_t CacheConfig::getAs()
{
return assoc;
}
void CacheConfig::setupTIO()
{
// setup tag, index, b
o = log2(blockSize);
index = log2(s / (blockSize * assoc));
tag = 32 - o - index;
offsetMask = (1 << o) - 1;
indexMask = ((1 << index) - 1) << o;
if (!victimSize)
return;
victimOffset = log2(blockSize);
victimIndex = 0;
victimTag = 32 - victimOffset - victimIndex;
victimAsso = victimSize / blockSize;
vom = (1 << victimOffset) - 1;
// vim = ((1<<victimIndex)-1) << victimOffset;
}
CacheIndex CacheConfig::parserVictimAddr(uint32_t addr) CacheIndex CacheConfig::parserVictimAddr(uint32_t addr)
{ {
uint32_t offset = addr & vom; uint32_t offset = addr & victimOffsetMask;
// uint32_t index = (addr & vim) >> victimOffset;
uint32_t tag = addr >> victimOffset; uint32_t tag = addr >> victimOffset;
return {tag, 0, offset, addr}; return {tag, 0, offset, addr};
} }
CacheIndex CacheConfig::AddrParser(uint32_t addr) CacheIndex CacheConfig::addrParser(uint32_t addr)
{ {
uint32_t offset = addr & offsetMask; uint32_t offset = addr & offsetMask;
uint32_t index = (addr & indexMask) >> o; uint32_t index = (addr & indexMask) >> this->offset;
uint32_t tag = addr >> (o + this->index); uint32_t tag = addr >> (this->offset + this->index);
return {tag, index, offset, addr}; return {tag, index, offset, addr};
} }
uint32_t CacheConfig::UnParser(uint32_t tag, CacheIndex tio) uint32_t CacheConfig::reparserAddr(uint32_t tag, CacheIndex tio)
{ {
return (tag << (o + index)) | (tio.index << o) | (tio.offset); return (tag << (this->offset + index)) | (tio.index << this->offset) | (tio.offset);
} }
uint32_t CacheConfig::UnParserVic(uint32_t tag, CacheIndex tio) uint32_t CacheConfig::reparserVictimAddr(uint32_t tag, CacheIndex tio)
{ {
return (tag << (victimOffset)) | (tio.offset); return (tag << (victimOffset)) | (tio.offset);
} }
@ -113,10 +88,10 @@ Cache::Cache(CacheConfig* config, Cache* nextCache)
this->config = config; this->config = config;
cache.resize(config->getMaxIndex()); cache.resize(config->getMaxIndex());
for (auto &b : cache) for (auto &b : cache)
b.resize(config->getAs()); b.resize(config->assoc);
if (config->victimSize) if (config->victimSize)
victimCache.resize(config->getVictimAs()); victimCache.resize(config->victimAssoc);
this->nextCache = nextCache; this->nextCache = nextCache;
} }
@ -126,20 +101,20 @@ void Cache::useCache(uint32_t rawAddr, bool isWrite)
isWrite ? writeCount++ : readCount++; isWrite ? writeCount++ : readCount++;
auto addr = config->AddrParser(rawAddr); auto addr = config->addrParser(rawAddr);
auto s = &cache[addr.index]; auto set = &cache[addr.index];
auto cl = find_if( auto cl = find_if(
s->begin(), set->begin(),
s->end(), set->end(),
[=](const Block &b) [=](const Block &b)
{ {
return b.valid && b.tag == addr.tag; return b.valid && b.tag == addr.tag;
}); });
if (cl != s->end()) if (cl != set->end())
{ {
for (auto &b : (*s)) for (auto &b : (*set))
b.lru += (b.lru < cl->lru); b.lru += (b.lru < cl->lru);
cl->lru = 0; cl->lru = 0;
cl->dirty |= isWrite; cl->dirty |= isWrite;
@ -148,19 +123,19 @@ void Cache::useCache(uint32_t rawAddr, bool isWrite)
// Main Cache Miss // Main Cache Miss
cl = find_if( cl = find_if(
s->begin(), set->begin(),
s->end(), set->end(),
[](const Block &b) [](const Block &b)
{ {
return !b.valid; return !b.valid;
}); });
if (cl == s->end()) if (cl == set->end())
{ {
// Replace // Replace
cl = max_element( cl = max_element(
s->begin(), set->begin(),
s->end()); set->end());
} }
if (!victimCache.size()) if (!victimCache.size())
@ -174,7 +149,7 @@ void Cache::useCache(uint32_t rawAddr, bool isWrite)
writeBack++; writeBack++;
if (nextCache != nullptr) if (nextCache != nullptr)
{ {
nextCache->useCache(config->UnParser(cl->tag, addr), true); nextCache->useCache(config->reparserAddr(cl->tag, addr), true);
} }
} }
@ -184,7 +159,7 @@ void Cache::useCache(uint32_t rawAddr, bool isWrite)
nextCache->useCache(rawAddr, false); nextCache->useCache(rawAddr, false);
} }
for (auto &b : (*s)) for (auto &b : (*set))
b.lru++; b.lru++;
*cl = {addr.tag, 0, isWrite, true}; *cl = {addr.tag, 0, isWrite, true};
} }
@ -209,10 +184,10 @@ void Cache::useCache(uint32_t rawAddr, bool isWrite)
{ {
for (auto &b : *vcp) for (auto &b : *vcp)
b.lru += (b.lru < tmp.lru); b.lru += (b.lru < tmp.lru);
*vic = {config->parserVictimAddr(config->UnParser(cl->tag, addr)).tag, 0, cl->dirty, true}; *vic = {config->parserVictimAddr(config->reparserAddr(cl->tag, addr)).tag, 0, cl->dirty, true};
} }
for (auto &b : (*s)) for (auto &b : (*set))
b.lru++; b.lru++;
*cl = {addr.tag, 0, isWrite || tmp.dirty, true}; *cl = {addr.tag, 0, isWrite || tmp.dirty, true};
exchange++; exchange++;
@ -227,7 +202,7 @@ void Cache::useCache(uint32_t rawAddr, bool isWrite)
{ {
nextCache->useCache(rawAddr, false); nextCache->useCache(rawAddr, false);
} }
for (auto &b : (*s)) for (auto &b : (*set))
b.lru++; b.lru++;
*cl = {addr.tag, 0, isWrite, true}; *cl = {addr.tag, 0, isWrite, true};
return; return;
@ -251,15 +226,15 @@ void Cache::useCache(uint32_t rawAddr, bool isWrite)
writeBack++; writeBack++;
if (nextCache != nullptr) if (nextCache != nullptr)
{ {
nextCache->useCache(config->UnParserVic(vic->tag, vaddr), true); nextCache->useCache(config->reparserVictimAddr(vic->tag, vaddr), true);
} }
} }
} }
for (auto &b : *vcp) for (auto &b : *vcp)
b.lru++; b.lru++;
*vic = {config->parserVictimAddr(config->UnParser(cl->tag, addr)).tag, 0, cl->dirty, true}; *vic = {config->parserVictimAddr(config->reparserAddr(cl->tag, addr)).tag, 0, cl->dirty, true};
for (auto &b : (*s)) for (auto &b : (*set))
b.lru++; b.lru++;
*cl = {addr.tag, 0, isWrite, true}; *cl = {addr.tag, 0, isWrite, true};
if (nextCache != nullptr) if (nextCache != nullptr)
@ -273,7 +248,7 @@ void Cache::useCache(uint32_t rawAddr, bool isWrite)
void Cache::printCache() void Cache::printCache()
{ {
if (!this->config->Size()) if (!this->config->size)
return; return;
cout << "===== " << this->config->level << " contents =====" << endl; cout << "===== " << this->config->level << " contents =====" << endl;
for (unsigned i = 0; i != this->cache.size(); i++) for (unsigned i = 0; i != this->cache.size(); i++)
@ -317,4 +292,7 @@ double Cache::getAAT()
return HT + (MP * MR); return HT + (MP * MR);
} }
int Cache::getCommunication() { return readMiss + writeMiss + writeBack; } int Cache::getCommunication()
{
return readMiss + writeMiss + writeBack;
}

35
cache/Project1/Proj1-2/Proj1-2/src/cache.h vendored
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@ -19,17 +19,17 @@ public:
string level; string level;
int blockSize; int blockSize;
int s; // Size int size;
int assoc; // Assoc int assoc;
int replicementPolicy; int replicementPolicy;
int writePolicy; int writePolicy;
int victimSize; int victimSize;
int victimAsso; int victimAssoc;
int tag; // tag bit int tag;
int index; // index int index;
int o; // offset int offset;
uint32_t offsetMask; uint32_t offsetMask;
uint32_t indexMask; uint32_t indexMask;
@ -38,29 +38,22 @@ public:
int victimIndex; int victimIndex;
int victimOffset; int victimOffset;
uint32_t vom; // victim offset mask uint32_t victimOffsetMask;
uint32_t vim; // victim index mask uint32_t victimIndexMask;
CacheConfig(); CacheConfig(int blockSize, int size, int assoc, int victimSize, int replicementPolicy, int writePolicy, string level);
CacheConfig(int blockSize, int size, int ass, int vis, int rep, int wrp, string l);
double getHT(); double getHT();
double getHT2(); double getHT2();
double getMP(); double getMP();
int log2(uint32_t x); int log2(uint32_t x);
uint32_t getMaxIndex(); uint32_t getMaxIndex();
uint32_t getVictimAs();
uint32_t getAs();
void setupTIO();
CacheIndex parserVictimAddr(uint32_t addr); CacheIndex parserVictimAddr(uint32_t addr);
CacheIndex AddrParser(uint32_t addr); CacheIndex addrParser(uint32_t addr);
uint32_t UnParser(uint32_t tag, CacheIndex tio); uint32_t reparserAddr(uint32_t tag, CacheIndex tio);
uint32_t UnParserVic(uint32_t tag, CacheIndex tio); uint32_t reparserVictimAddr(uint32_t tag, CacheIndex tio);
int getBlockSize();
int Size();
int Assoc();
int ReplicementPolicy();
int WritePolicy();
}; };
struct Block struct Block

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cache/Project1/Proj1-2/Proj1-2/src/sim_cache vendored
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