diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..77da5d8 --- /dev/null +++ b/.gitignore @@ -0,0 +1 @@ +cache/Project1/Proj1-2/Proj1-2/src/*.o diff --git a/cache/Project1/Proj1-2/Proj1-2/.vscode/settings.json b/cache/Project1/Proj1-2/Proj1-2/.vscode/settings.json index 56ce1cb..9c86ebe 100644 --- a/cache/Project1/Proj1-2/Proj1-2/.vscode/settings.json +++ b/cache/Project1/Proj1-2/Proj1-2/.vscode/settings.json @@ -63,6 +63,55 @@ "vector": "cpp", "ostream": "cpp", "iosfwd": "cpp", - "iomanip": "cpp" + "iomanip": "cpp", + "algorithm": "cpp", + "atomic": "cpp", + "bit": "cpp", + "bitset": "cpp", + "cctype": "cpp", + "charconv": "cpp", + "clocale": "cpp", + "cmath": "cpp", + "compare": "cpp", + "concepts": "cpp", + "cstddef": "cpp", + "cstdint": "cpp", + "cstdio": "cpp", + "cstdlib": "cpp", + "cstring": "cpp", + "ctime": "cpp", + "cwchar": "cpp", + "exception": "cpp", + "format": "cpp", + "initializer_list": "cpp", + "ios": "cpp", + "istream": "cpp", + "iterator": "cpp", + "limits": "cpp", + "locale": "cpp", + "memory": "cpp", + "new": "cpp", + "optional": "cpp", + "stdexcept": "cpp", + "streambuf": "cpp", + "string": "cpp", + "system_error": "cpp", + "tuple": "cpp", + "type_traits": "cpp", + "typeinfo": "cpp", + "utility": "cpp", + "xfacet": "cpp", + "xiosbase": "cpp", + "xlocale": "cpp", + "xlocbuf": "cpp", + "xlocinfo": "cpp", + "xlocmes": "cpp", + "xlocmon": "cpp", + "xlocnum": "cpp", + "xloctime": "cpp", + "xmemory": "cpp", + "xstring": "cpp", + "xtr1common": "cpp", + "xutility": "cpp" } } \ No newline at end of file diff --git a/cache/Project1/Proj1-2/Proj1-2/src/3020202184_刘锦帆.pdf b/cache/Project1/Proj1-2/Proj1-2/src/3020202184_刘锦帆.pdf deleted file mode 100644 index ed764b4..0000000 Binary files a/cache/Project1/Proj1-2/Proj1-2/src/3020202184_刘锦帆.pdf and /dev/null differ diff --git a/cache/Project1/Proj1-2/Proj1-2/src/NewCache.cc b/cache/Project1/Proj1-2/Proj1-2/src/NewCache.cc index 6db6679..1bfadd5 100644 --- a/cache/Project1/Proj1-2/Proj1-2/src/NewCache.cc +++ b/cache/Project1/Proj1-2/Proj1-2/src/NewCache.cc @@ -30,13 +30,58 @@ NewCache::NewCache(Config *config) this->config = config; if (config->L2_size > 0) { - Cache *l2 = new Cache(config->blockSize, config->L2_size, config->L2_assoc, 0, "L2"); - cache = new Cache(config->blockSize, config->L1_size, config->L1_assoc, config->victimCacheSize, l2, "L1"); - m = new Monitor(cache->GetStatis(), l2->GetStatis(), config->L2_size, config->victimCacheSize); + Cache *L2 = new Cache(config->blockSize, config->L2_size, config->L2_assoc, 0, "L2"); + cache = new Cache(config->blockSize, config->L1_size, config->L1_assoc, config->victimCacheSize, L2, "L1"); + l1 = cache, l2 = L2; + Has2 = config->L2_size, HasV = config->victimCacheSize; + } else { cache = new Cache(config->blockSize, config->L1_size, config->L1_assoc, config->victimCacheSize, nullptr, "L1"); - m = new Monitor(cache->GetStatis(), nullptr, config->L2_size, config->victimCacheSize); + l1 = cache, l2 = nullptr; + Has2 = config->L2_size, HasV = config->victimCacheSize; } } + +void NewCache::printMonitor() +{ + cout << "====== Simulation results (raw) ======" << endl; + cout << setw(38) << "a. number of L1 reads: " << this->l1->r << endl; + cout << setw(38) << "b. number of L1 read misses: " << this->l1->rm << endl; + cout << "c. number of L1 writes: " << this->l1->w << endl; + cout << setw(38) << "d. number of L1 write misses: " << this->l1->wm << endl; + cout << setw(38) << "e. L1 miss rate: " << fixed << setprecision(4) << this->l1->getMR() << endl; + cout << setw(38) << "f. number of swaps: " << this->l1->ex << endl; + cout << setw(38) << "g. number of victim cache writeback: " << (this->HasV ? this->l1->wb : 0) << endl; + if (this->Has2) + { + cout << setw(38) << "h. number of L2 reads: " << this->l2->r << endl; + cout << setw(38) << "i. number of L2 read misses: " << this->l2->rm << endl; + cout << setw(38) << "j. number of L2 writes: " << this->l2->w << endl; + cout << setw(38) << "k. number of L2 write misses: " << this->l2->wm << endl; + cout << setw(38) << "l. L2 miss rate: " << fixed << setprecision((this->Has2) ? 4 : 0) << this->l2->getMR2() << endl; + cout << setw(38) << "m. number of L2 writebacks: " << this->l2->wb << endl; + cout << setw(38) << "n. total memory traffic: " << (this->l2->rm + this->l2->wm + this->l2->wb) << endl; + cout << "==== Simulation results (performance) ====" << endl; + double HT1 = this->l1->config.getHT(), MR1 = this->l1->getMR(); + double HT2 = this->l2->config.getHT2(), MR2 = this->l2->getMR2(); + double MP = this->l2->config.getMP(); + cout << setw(32) << "1. average access time:" << fixed << setprecision(4) << HT1 + (MR1 * (HT2 + MR2 * MP)) << " ns" << endl; + } + else + { + cout << setw(38) << "h. number of L2 reads: " << 0 << endl; + cout << setw(38) << "i. number of L2 read misses: " << 0 << endl; + cout << setw(38) << "j. number of L2 writes: " << 0 << endl; + cout << setw(38) << "k. number of L2 write misses: " << 0 << endl; + cout << setw(38) << "l. L2 miss rate: " << 0 << endl; + cout << setw(38) << "m. number of L2 writebacks: " << 0 << endl; + cout << setw(38) << "n. total memory traffic: " << (this->l1->rm + this->l1->wm + this->l1->wb) << endl; + cout << "==== Simulation results (performance) ====" << endl; + double ht = this->l1->config.getHT(); + double mp = this->l1->config.getMP(); + double mr = (this->l1->rm + this->l1->wm) / (double)(this->l1->r + this->l1->w); + cout << setw(32) << "1. average access time:" << fixed << setprecision(4) << ht + mr * mp << " ns" << endl; + } +} \ No newline at end of file diff --git a/cache/Project1/Proj1-2/Proj1-2/src/NewCache.h b/cache/Project1/Proj1-2/Proj1-2/src/NewCache.h index 4fde946..189e2c3 100644 --- a/cache/Project1/Proj1-2/Proj1-2/src/NewCache.h +++ b/cache/Project1/Proj1-2/Proj1-2/src/NewCache.h @@ -27,9 +27,10 @@ class NewCache public: Config *config; Cache *cache; - Monitor *m; - NewCache(Config *config); - ~NewCache(); + Cache *l1, *l2; + bool Has2, HasV; + NewCache(Config *config); + void printMonitor(); }; diff --git a/cache/Project1/Proj1-2/Proj1-2/src/NewCache.o b/cache/Project1/Proj1-2/Proj1-2/src/NewCache.o index 1962f08..527a653 100644 Binary files a/cache/Project1/Proj1-2/Proj1-2/src/NewCache.o and b/cache/Project1/Proj1-2/Proj1-2/src/NewCache.o differ diff --git a/cache/Project1/Proj1-2/Proj1-2/src/cache.cc b/cache/Project1/Proj1-2/Proj1-2/src/cache.cc index cf38ee1..1837db7 100644 --- a/cache/Project1/Proj1-2/Proj1-2/src/cache.cc +++ b/cache/Project1/Proj1-2/Proj1-2/src/cache.cc @@ -6,13 +6,14 @@ #include using namespace std; -int CacheParam::getBlockSize() { return blockSize; } -int CacheParam::Size() { return s; } -int CacheParam::Assoc() { return assoc; } -int CacheParam::ReplicementPolicy() { return replicementPolicy; } -int CacheParam::WritePolicy() { return writePolicy; } -CacheParam::CacheParam(){} -CacheParam::CacheParam(int blockSize, int size, int ass, int vis, int rep, int wrp) +int CacheConfig::getBlockSize() { return blockSize; } +int CacheConfig::Size() { return s; } +int CacheConfig::Assoc() { return assoc; } +int CacheConfig::ReplicementPolicy() { return replicementPolicy; } +int CacheConfig::WritePolicy() { return writePolicy; } + +CacheConfig::CacheConfig() {} +CacheConfig::CacheConfig(int blockSize, int size, int ass, int vis, int rep, int wrp) { this->blockSize = blockSize; this->s = size; @@ -22,42 +23,42 @@ CacheParam::CacheParam(int blockSize, int size, int ass, int vis, int rep, int w this->writePolicy = wrp; setupTIO(); } -double CacheParam::GetHT() +double CacheConfig::getHT() { return 0.25 + 2.5 * (s / (512.0 * 1024)) + 0.025 * (blockSize / 16.0) + 0.025 * assoc; } -double CacheParam::GetHT2() +double CacheConfig::getHT2() { return 2.5 + 2.5 * (s / (512.0 * 1024)) + 0.025 * (blockSize / 16.0) + 0.025 * assoc; } -double CacheParam::GetMP() +double CacheConfig::getMP() { return 20 + 0.5 * (blockSize / 16.0); } -int CacheParam::log2_floor(uint32_t x) +int CacheConfig::log2_floor(uint32_t x) { return x == 0 ? -1 : 31 - __builtin_clz(x); } -uint32_t CacheParam::GetMaxIndex() +uint32_t CacheConfig::getMaxIndex() { return (1 << i); } -uint32_t CacheParam::GetVictimAs() +uint32_t CacheConfig::getVictimAs() { return victimAsso; } -uint32_t CacheParam::GetAs() +uint32_t CacheConfig::getAs() { return assoc; } -void CacheParam::setupTIO() +void CacheConfig::setupTIO() { // setup t, i, b o = log2_floor(blockSize); @@ -79,7 +80,7 @@ void CacheParam::setupTIO() // vim = ((1<> vo; @@ -87,7 +88,7 @@ CacheTIO CacheParam::VictimAddrParser(uint32_t addr) return {tag, 0, offset, addr}; } -CacheTIO CacheParam::AddrParser(uint32_t addr) +CacheTIO CacheConfig::AddrParser(uint32_t addr) { uint32_t offset = addr & om; uint32_t index = (addr & im) >> o; @@ -95,12 +96,12 @@ CacheTIO CacheParam::AddrParser(uint32_t addr) return {tag, index, offset, addr}; } -uint32_t CacheParam::UnParser(uint32_t tag, CacheTIO tio) +uint32_t CacheConfig::UnParser(uint32_t tag, CacheTIO tio) { return (tag << (o + i)) | (tio.index << o) | (tio.offset); } -uint32_t CacheParam::UnParserVic(uint32_t tag, CacheTIO tio) +uint32_t CacheConfig::UnParserVic(uint32_t tag, CacheTIO tio) { return (tag << (vo)) | (tio.offset); } @@ -108,38 +109,36 @@ uint32_t CacheParam::UnParserVic(uint32_t tag, CacheTIO tio) Cache::Cache(int blockSize, int s, int assoc, int victimSize, string l, int replicementPolicy, int writePolicy) { - p = CacheParam(blockSize, s, assoc, victimSize, replicementPolicy, writePolicy); - st.SetCP(&p); - c.resize(p.GetMaxIndex()); + config = CacheConfig(blockSize, s, assoc, victimSize, replicementPolicy, writePolicy); + c.resize(config.getMaxIndex()); this->level = l; for (auto &b : c) - b.resize(p.GetAs()); + b.resize(config.getAs()); if (victimSize) - vc.resize(p.GetVictimAs()); + vc.resize(config.getVictimAs()); } Cache::Cache(int blockSize, int s, int assoc, int victimSize, Cache *n, string l, int replicementPolicy, int writePolicy) { - p = CacheParam(blockSize, s, assoc, victimSize, replicementPolicy, writePolicy); - st.SetCP(&p); - c.resize(p.GetMaxIndex()); + config = CacheConfig(blockSize, s, assoc, victimSize, replicementPolicy, writePolicy); + c.resize(config.getMaxIndex()); for (auto &b : c) - b.resize(p.GetAs()); + b.resize(config.getAs()); if (victimSize) - vc.resize(p.GetVictimAs()); + vc.resize(config.getVictimAs()); NextCache = n; level = l; } -void Cache::Visit(uint32_t rawAddr, bool isWrite) +void Cache::useCache(uint32_t rawAddr, bool isWrite) { - isWrite ? st.Write() : st.Read(); + isWrite ? Write() : Read(); - auto addr = p.AddrParser(rawAddr); + auto addr = config.AddrParser(rawAddr); auto s = &c[addr.index]; // Find in Cache @@ -180,23 +179,23 @@ void Cache::Visit(uint32_t rawAddr, bool isWrite) if (!vc.size()) { - isWrite ? st.WriteMiss() : st.ReadMiss(); + isWrite ? WriteMiss() : ReadMiss(); // No Victim Cache if (cl->v && cl->d) { // Write to the L2 or Disk - st.WriteBack(); + WriteBack(); if (NextCache != nullptr) { - NextCache->Visit(p.UnParser(cl->tag, addr), true); + NextCache->useCache(config.UnParser(cl->tag, addr), true); } } if (NextCache != nullptr) { // 2. Find it from Next Level - NextCache->Visit(rawAddr, false); + NextCache->useCache(rawAddr, false); } for (auto &b : (*s)) @@ -209,7 +208,7 @@ void Cache::Visit(uint32_t rawAddr, bool isWrite) // Miss Write or Read Miss, Go to Next Level // 1. Find it from Victim Cache - auto vaddr = p.VictimAddrParser(rawAddr); + auto vaddr = config.VictimAddrParser(rawAddr); auto vcp = &vc; auto vic = find_if( @@ -228,25 +227,25 @@ void Cache::Visit(uint32_t rawAddr, bool isWrite) { for (auto &b : *vcp) b.lru += (b.lru < tmp.lru); - *vic = {p.VictimAddrParser(p.UnParser(cl->tag, addr)).tag, 0, cl->d, true}; + *vic = {config.VictimAddrParser(config.UnParser(cl->tag, addr)).tag, 0, cl->d, true}; } for (auto &b : (*s)) b.lru++; *cl = {addr.tag, 0, isWrite || tmp.d, true}; - st.Exchange(); + Exchange(); return; } // X. Victim Cache Miss! - isWrite ? st.WriteMiss() : st.ReadMiss(); + isWrite ? WriteMiss() : ReadMiss(); if (!cl->v) { if (NextCache != nullptr) { // 2. Find it from Next Level - NextCache->Visit(rawAddr, false); + NextCache->useCache(rawAddr, false); } // Empty Level 1 for (auto &b : (*s)) @@ -271,17 +270,17 @@ void Cache::Visit(uint32_t rawAddr, bool isWrite) vcp->end()); if (vic->v && vic->d) { - st.WriteBack(); + WriteBack(); if (NextCache != nullptr) { - NextCache->Visit(p.UnParserVic(vic->tag, vaddr), true); + NextCache->useCache(config.UnParserVic(vic->tag, vaddr), true); } } } // New Victim Cache for (auto &b : *vcp) b.lru++; - *vic = {p.VictimAddrParser(p.UnParser(cl->tag, addr)).tag, 0, cl->d, true}; + *vic = {config.VictimAddrParser(config.UnParser(cl->tag, addr)).tag, 0, cl->d, true}; for (auto &b : (*s)) b.lru++; @@ -289,9 +288,38 @@ void Cache::Visit(uint32_t rawAddr, bool isWrite) if (NextCache != nullptr) { // 2. Find it from Next Level - NextCache->Visit(rawAddr, false); + NextCache->useCache(rawAddr, false); } } return; } + +void Cache::printCache() +{ + if (!this->config.Size()) + return; + cout << "===== " << this->level << " contents =====" << endl; + for (unsigned i = 0; i != this->c.size(); i++) + { + cout << "set " << i << ": "; + auto temp = this->c[i]; + stable_sort(temp.begin(), temp.end()); + for (auto b : temp) + cout << hex << b.tag << (b.d ? " D " : " "); + cout << endl + << dec; + } + if (this->vc.size()) + { + cout << "===== Victim Cache contents =====" << endl; + cout << "set 0: "; + auto temp = this->vc; + stable_sort(temp.begin(), temp.end()); + for (auto b : temp) + cout << hex << b.tag << (b.d ? " D " : " "); + cout << endl + << dec; + } +} + diff --git a/cache/Project1/Proj1-2/Proj1-2/src/cache.h b/cache/Project1/Proj1-2/Proj1-2/src/cache.h index 47e173a..be243d5 100644 --- a/cache/Project1/Proj1-2/Proj1-2/src/cache.h +++ b/cache/Project1/Proj1-2/Proj1-2/src/cache.h @@ -13,7 +13,7 @@ struct CacheTIO uint32_t tag, index, offset, rAddr; }; -class CacheParam +class CacheConfig { public: int blockSize; // Block Size @@ -39,16 +39,16 @@ public: uint32_t vom; // victim offset mask uint32_t vim; // victim index mask - CacheParam(); - CacheParam(int blockSize, int size, int ass, int vis, int rep, int wrp); + CacheConfig(); + CacheConfig(int blockSize, int size, int ass, int vis, int rep, int wrp); - double GetHT(); - double GetHT2(); - double GetMP(); + double getHT(); + double getHT2(); + double getMP(); int log2_floor(uint32_t x); - uint32_t GetMaxIndex(); - uint32_t GetVictimAs(); - uint32_t GetAs(); + uint32_t getMaxIndex(); + uint32_t getVictimAs(); + uint32_t getAs(); void setupTIO(); CacheTIO VictimAddrParser(uint32_t addr); CacheTIO AddrParser(uint32_t addr); @@ -68,135 +68,13 @@ struct Block bool d = false; // dirty bool v = false; // valid bool operator<(const Block &t) const { return lru < t.lru; } - void printBlock() - { - cout << "{tag:" << this->tag << ", LRU:" << this->lru << ", Dirty:" << this->d << ", Valid:" << this->v << "}"; - } }; -class Statistic -{ -public: - int r = 0; // Read Count - int rm = 0; // Read Miss - int w = 0; // Write Count - int wm = 0; // Write Miss - int wb = 0; // Write Back - int ex = 0; // Exchange (between L1 and Victim) - - CacheParam *p; - -public: - void SetCP(CacheParam *cp) { p = cp; } - - void Read() { r++; } - void ReadMiss() { rm++; } - void Write() { w++; } - void WriteMiss() { wm++; } - void WriteBack() { wb++; } - void Exchange() { ex++; } - int GetCommunication() { return rm + wm + wb; } - - double GetMR() - { - return (double)(rm + wm) / (double)(r + w); - } - - double GetMR2() - { - return (double)(rm) / (double)(r); - } - - double GetAAT() - { - double HT = p->GetHT(); - double MP = p->GetMP(); - double MR = GetMR(); - return HT + (MP * MR); - } - - friend ostream &operator<<(ostream &cout, const Statistic &st) - { - - cout << "\n ====== Simulation results (raw) ======\n"; - cout << " a. number of L1 reads:" << setw(16) << st.r << endl; - cout << " b. number of L1 read misses:" << setw(10) << st.rm << endl; - cout << " c. number of L1 writes:" << setw(15) << st.w << endl; - cout << " d. number of L1 write misses:" << setw(9) << st.wm << endl; - double mr = (st.rm + st.wm) / (double)(st.r + st.w); - cout << " e. L1 miss rate:" << setw(22) << fixed << setprecision(4) << mr << endl; - cout << " f. number of writebacks from L1:" << setw(6) << st.wb << endl; - cout << " g. total memory traffic:" << setw(14) << ((st.p->WritePolicy()) ? (st.rm + st.w) : (st.rm + st.wm + st.wb)); - cout << "\n\n ==== Simulation results (performance) ====\n"; - double ht = st.p->GetHT(); - double mp = st.p->GetMP(); - cout << " 1. average access time:" << setw(15) << ht + mr * mp << " ns"; - return cout; - } -}; - -class Monitor -{ - -public: - Statistic *l1, *l2; - bool Has2, HasV; - Monitor() {} - Monitor(Statistic *s1, Statistic *s2, bool h2, bool hv) - { - l1 = s1, l2 = s2; - Has2 = h2, HasV = hv; - } - friend ostream &operator<<(ostream &cout, Monitor &m) - { - cout << "====== Simulation results (raw) ======" << endl; - cout << setw(38) << "a. number of L1 reads: " << m.l1->r << endl; - cout << setw(38) << "b. number of L1 read misses: " << m.l1->rm << endl; - cout << "c. number of L1 writes: " << m.l1->w << endl; - cout << setw(38) << "d. number of L1 write misses: " << m.l1->wm << endl; - cout << setw(38) << "e. L1 miss rate: " << fixed << setprecision(4) << m.l1->GetMR() << endl; - cout << setw(38) << "f. number of swaps: " << m.l1->ex << endl; - cout << setw(38) << "g. number of victim cache writeback: " << (m.HasV ? m.l1->wb : 0) << endl; - if (m.Has2) - { - cout << setw(38) << "h. number of L2 reads: " << m.l2->r << endl; - cout << setw(38) << "i. number of L2 read misses: " << m.l2->rm << endl; - cout << setw(38) << "j. number of L2 writes: " << m.l2->w << endl; - cout << setw(38) << "k. number of L2 write misses: " << m.l2->wm << endl; - cout << setw(38) << "l. L2 miss rate: " << fixed << setprecision((m.Has2) ? 4 : 0) << m.l2->GetMR2() << endl; - cout << setw(38) << "m. number of L2 writebacks: " << m.l2->wb << endl; - cout << setw(38) << "n. total memory traffic: " << (m.l2->rm + m.l2->wm + m.l2->wb) << endl; - cout << "==== Simulation results (performance) ====" << endl; - double HT1 = m.l1->p->GetHT(), MR1 = m.l1->GetMR(); - double HT2 = m.l2->p->GetHT2(), MR2 = m.l2->GetMR2(); - double MP = m.l2->p->GetMP(); - cout << setw(32) << "1. average access time:" << fixed << setprecision(4) << HT1 + (MR1 * (HT2 + MR2 * MP)) << " ns" << endl; - } - else - { - cout << setw(38) << "h. number of L2 reads: " << 0 << endl; - cout << setw(38) << "i. number of L2 read misses: " << 0 << endl; - cout << setw(38) << "j. number of L2 writes: " << 0 << endl; - cout << setw(38) << "k. number of L2 write misses: " << 0 << endl; - cout << setw(38) << "l. L2 miss rate: " << 0 << endl; - cout << setw(38) << "m. number of L2 writebacks: " << 0 << endl; - cout << setw(38) << "n. total memory traffic: " << (m.l1->rm + m.l1->wm + m.l1->wb) << endl; - cout << "==== Simulation results (performance) ====" << endl; - double ht = m.l1->p->GetHT(); - double mp = m.l1->p->GetMP(); - double mr = (m.l1->rm + m.l1->wm) / (double)(m.l1->r + m.l1->w); - cout << setw(32) << "1. average access time:" << fixed << setprecision(4) << ht + mr * mp << " ns" << endl; - } - - return cout; - } -}; class Cache { public: - CacheParam p; - Statistic st; + CacheConfig config; vector> c; // Cache vector vc; // Victim Cache @@ -205,43 +83,44 @@ public: Cache *NextCache = nullptr; + + int r = 0; // Read Count + int rm = 0; // Read Miss + int w = 0; // Write Count + int wm = 0; // Write Miss + int wb = 0; // Write Back + int ex = 0; // Exchange (between L1 and Victim) + + void Read() { r++; } + void ReadMiss() { rm++; } + void Write() { w++; } + void WriteMiss() { wm++; } + void WriteBack() { wb++; } + void Exchange() { ex++; } + int getCommunication() { return rm + wm + wb; } + + double getMR() + { + return (double)(rm + wm) / (double)(r + w); + } + + double getMR2() + { + return (double)(rm) / (double)(r); + } + + double getAAT() + { + double HT = config.getHT(); + double MP = config.getMP(); + double MR = getMR(); + return HT + (MP * MR); + } + + Cache(int blockSize, int s, int assoc, int victimSize, string l = "L1", int replicementPolicy = LRU, int writePolicy = LFU); Cache(int blockSize, int s, int assoc, int victimSize, Cache *n = nullptr, string l = "L1", int replicementPolicy = LRU, int writePolicy = LFU); - ~Cache() - { - delete NextCache; - } - - Statistic *GetStatis() { return &st; } - - void Visit(uint32_t rawAddr, bool isWrite); - - void printCache() - { - if (!this->p.Size()) - return; - cout << "===== " << this->level << " contents =====" << endl; - for (unsigned i = 0; i != this->c.size(); i++) - { - cout << "set " << i << ": "; - auto temp = this->c[i]; - stable_sort(temp.begin(), temp.end()); - for (auto b : temp) - cout << hex << b.tag << (b.d ? " D " : " "); - cout << endl - << dec; - } - if (this->vc.size()) - { - cout << "===== Victim Cache contents =====" << endl; - cout << "set 0: "; - auto temp = this->vc; - stable_sort(temp.begin(), temp.end()); - for (auto b : temp) - cout << hex << b.tag << (b.d ? " D " : " "); - cout << endl - << dec; - } - } + void useCache(uint32_t rawAddr, bool isWrite); + void printCache(); }; diff --git a/cache/Project1/Proj1-2/Proj1-2/src/cache.o b/cache/Project1/Proj1-2/Proj1-2/src/cache.o index 79366a6..bcf492a 100644 Binary files a/cache/Project1/Proj1-2/Proj1-2/src/cache.o and b/cache/Project1/Proj1-2/Proj1-2/src/cache.o differ diff --git a/cache/Project1/Proj1-2/Proj1-2/src/main.cc b/cache/Project1/Proj1-2/Proj1-2/src/main.cc index 3a2be2d..8481345 100644 --- a/cache/Project1/Proj1-2/Proj1-2/src/main.cc +++ b/cache/Project1/Proj1-2/Proj1-2/src/main.cc @@ -25,21 +25,28 @@ int main(int argc, char *argv[]) unsigned addr; while (getline(trace, line) && (istringstream(line) >> op >> hex >> addr)) { - newCache->cache->Visit(addr, op == 'w'); + newCache->cache->useCache(addr, op == 'w'); } trace.close(); } - catch (const std::exception &e) + catch (...) { cout << "run err." << endl; - std::cerr << e.what() << '\n'; } // 输出 - config->printConfig(); - newCache->cache->printCache(); - if (newCache->m->Has2) - (newCache->cache->NextCache)->printCache(); - cout << (*newCache->m); + try + { + config->printConfig(); + newCache->cache->printCache(); + if (newCache->Has2) + (newCache->cache->NextCache)->printCache(); + newCache->printMonitor(); + } + catch (...) + { + cout << "output err." << endl; + } + return 0; } diff --git a/cache/Project1/Proj1-2/Proj1-2/src/main.o b/cache/Project1/Proj1-2/Proj1-2/src/main.o index 3454d51..0eb7d3b 100644 Binary files a/cache/Project1/Proj1-2/Proj1-2/src/main.o and b/cache/Project1/Proj1-2/Proj1-2/src/main.o differ diff --git a/cache/Project1/Proj1-2/Proj1-2/src/sim_cache b/cache/Project1/Proj1-2/Proj1-2/src/sim_cache index e510833..72ad418 100644 Binary files a/cache/Project1/Proj1-2/Proj1-2/src/sim_cache and b/cache/Project1/Proj1-2/Proj1-2/src/sim_cache differ diff --git a/cache/TJU-2023-Computer-Organization/Proj1-1/Proj1-1/src/cache.cc b/cache/TJU-2023-Computer-Organization/Proj1-1/Proj1-1/src/cache.cc index 57888dd..978f065 100644 --- a/cache/TJU-2023-Computer-Organization/Proj1-1/Proj1-1/src/cache.cc +++ b/cache/TJU-2023-Computer-Organization/Proj1-1/Proj1-1/src/cache.cc @@ -14,14 +14,14 @@ Cache::Cache(int argc, char *argv[]){ } void Cache::Read(uint32_t rawAddr){ - return Visit(rawAddr, false); + return useCache(rawAddr, false); } void Cache::Write(uint32_t rawAddr){ - return Visit(rawAddr, true); + return useCache(rawAddr, true); } -void Cache::Visit(uint32_t rawAddr, bool isWrite){ +void Cache::useCache(uint32_t rawAddr, bool isWrite){ isWrite ? st.Write() : st.Read(); @@ -101,7 +101,7 @@ void Cache::Run(){ char op; unsigned addr; while(getline(trace, line) && (istringstream(line) >> op >> hex >> addr)) { - Visit(addr, op == 'w'); + useCache(addr, op == 'w'); } trace.close(); } diff --git a/cache/TJU-2023-Computer-Organization/Proj1-1/Proj1-1/src/cache.h b/cache/TJU-2023-Computer-Organization/Proj1-1/Proj1-1/src/cache.h index c3e3479..5960441 100644 --- a/cache/TJU-2023-Computer-Organization/Proj1-1/Proj1-1/src/cache.h +++ b/cache/TJU-2023-Computer-Organization/Proj1-1/Proj1-1/src/cache.h @@ -44,7 +44,7 @@ public: void Write(uint32_t addr); void Read(uint32_t addr); - void Visit(uint32_t addr, bool isWrite); + void useCache(uint32_t addr, bool isWrite); friend ostream& operator<<(ostream& os, Cache& c){ diff --git a/cache/TJU-2023-Computer-Organization/Proj1-2/Proj1-2/src/.vscode/c_cpp_properties.json b/cache/TJU-2023-Computer-Organization/Proj1-2/Proj1-2/src/.vscode/c_cpp_properties.json new file mode 100644 index 0000000..cea4d3f --- /dev/null +++ b/cache/TJU-2023-Computer-Organization/Proj1-2/Proj1-2/src/.vscode/c_cpp_properties.json @@ -0,0 +1,18 @@ +{ + "configurations": [ + { + "name": "windows-gcc-x64", + "includePath": [ + "${workspaceFolder}/**" + ], + "compilerPath": "gcc", + "cStandard": "${default}", + "cppStandard": "${default}", + "intelliSenseMode": "windows-gcc-x64", + "compilerArgs": [ + "" + ] + } + ], + "version": 4 +} \ No newline at end of file diff --git a/cache/TJU-2023-Computer-Organization/Proj1-2/Proj1-2/src/.vscode/launch.json b/cache/TJU-2023-Computer-Organization/Proj1-2/Proj1-2/src/.vscode/launch.json new file mode 100644 index 0000000..ca05677 --- /dev/null +++ b/cache/TJU-2023-Computer-Organization/Proj1-2/Proj1-2/src/.vscode/launch.json @@ -0,0 +1,24 @@ +{ + "version": "0.2.0", + "configurations": [ + { + "name": "C/C++ Runner: Debug Session", + "type": "cppdbg", + "request": "launch", + "args": [], + "stopAtEntry": false, + "externalConsole": true, + "cwd": "d:/code/computer-organization/cache/TJU-2023-Computer-Organization/Proj1-2/Proj1-2/src", + "program": "d:/code/computer-organization/cache/TJU-2023-Computer-Organization/Proj1-2/Proj1-2/src/build/Debug/outDebug", + "MIMode": "gdb", + "miDebuggerPath": "gdb", + "setupCommands": [ + { + "description": "Enable pretty-printing for gdb", + "text": "-enable-pretty-printing", + "ignoreFailures": true + } + ] + } + ] +} \ No newline at end of file diff --git a/cache/TJU-2023-Computer-Organization/Proj1-2/Proj1-2/src/.vscode/settings.json b/cache/TJU-2023-Computer-Organization/Proj1-2/Proj1-2/src/.vscode/settings.json new file mode 100644 index 0000000..bb879da --- /dev/null +++ b/cache/TJU-2023-Computer-Organization/Proj1-2/Proj1-2/src/.vscode/settings.json @@ -0,0 +1,59 @@ +{ + "C_Cpp_Runner.cCompilerPath": "gcc", + "C_Cpp_Runner.cppCompilerPath": "g++", + "C_Cpp_Runner.debuggerPath": "gdb", + "C_Cpp_Runner.cStandard": "", + "C_Cpp_Runner.cppStandard": "", + "C_Cpp_Runner.msvcBatchPath": "C:/Program Files/Microsoft Visual Studio/VR_NR/Community/VC/Auxiliary/Build/vcvarsall.bat", + "C_Cpp_Runner.useMsvc": false, + "C_Cpp_Runner.warnings": [ + "-Wall", + "-Wextra", + "-Wpedantic", + "-Wshadow", + "-Wformat=2", + "-Wcast-align", + "-Wconversion", + "-Wsign-conversion", + "-Wnull-dereference" + ], + "C_Cpp_Runner.msvcWarnings": [ + "/W4", + "/permissive-", + "/w14242", + "/w14287", + "/w14296", + "/w14311", + "/w14826", + "/w44062", + "/w44242", + "/w14905", + "/w14906", + "/w14263", + "/w44265", + "/w14928" + ], + "C_Cpp_Runner.enableWarnings": true, + "C_Cpp_Runner.warningsAsError": false, + "C_Cpp_Runner.compilerArgs": [], + "C_Cpp_Runner.linkerArgs": [], + "C_Cpp_Runner.includePaths": [], + "C_Cpp_Runner.includeSearch": [ + "*", + "**/*" + ], + "C_Cpp_Runner.excludeSearch": [ + "**/build", + "**/build/**", + "**/.*", + "**/.*/**", + "**/.vscode", + "**/.vscode/**" + ], + "C_Cpp_Runner.useAddressSanitizer": false, + "C_Cpp_Runner.useUndefinedSanitizer": false, + "C_Cpp_Runner.useLeakSanitizer": false, + "C_Cpp_Runner.showCompilationTime": false, + "C_Cpp_Runner.useLinkTimeOptimization": false, + "C_Cpp_Runner.msvcSecureNoWarnings": false +} \ No newline at end of file diff --git a/cache/TJU-2023-Computer-Organization/Proj1-2/Proj1-2/src/README.md b/cache/TJU-2023-Computer-Organization/Proj1-2/Proj1-2/src/README.md index 16c56a8..8b18236 100644 --- a/cache/TJU-2023-Computer-Organization/Proj1-2/Proj1-2/src/README.md +++ b/cache/TJU-2023-Computer-Organization/Proj1-2/Proj1-2/src/README.md @@ -21,7 +21,7 @@ ## 伪代码 ```c++ -void Cache::Visit(uint32_t addr, bool isWrite){ +void Cache::useCache(uint32_t addr, bool isWrite){ if(IsDisk) return; C = cache[parser(addr).index]; if(C.Hit(addr, isWrite)){ @@ -37,13 +37,13 @@ void Cache::Visit(uint32_t addr, bool isWrite){ // Victim Cache Miss if(C.HasEmpty()){ // L1 has Idle Block - NextLevel.Visit(addr, false); + NextLevel.useCache(addr, false); C.Empty = Block(addr, isWrite); }else{ // L1 is FULL if(Vic.LRU.D) // Write Back Victim - NextLevel.Visit(Vic.LRU.Addr, true); - NextLevel.Visit(addr, false); + NextLevel.useCache(Vic.LRU.Addr, true); + NextLevel.useCache(addr, false); Vic.LRU = C.LRU; C.LRU = Block(addr, isWrite); } @@ -51,8 +51,8 @@ void Cache::Visit(uint32_t addr, bool isWrite){ }else{ // No Victim (L2) if(C.LRU.D) // Write Back - NextLevel.Visit(C.LRU.Addr, true); - NextLevel.Visit(addr, false); + NextLevel.useCache(C.LRU.Addr, true); + NextLevel.useCache(addr, false); C.LRU = Block(addr, isWrite); } } diff --git a/cache/TJU-2023-Computer-Organization/Proj1-2/Proj1-2/src/cache.cc b/cache/TJU-2023-Computer-Organization/Proj1-2/Proj1-2/src/cache.cc index 7d54024..057591a 100644 --- a/cache/TJU-2023-Computer-Organization/Proj1-2/Proj1-2/src/cache.cc +++ b/cache/TJU-2023-Computer-Organization/Proj1-2/Proj1-2/src/cache.cc @@ -32,14 +32,14 @@ Cache::Cache(int bs, int s, int as, int vs, Cache* n, string l, int rp, int wp){ } void Cache::Read(uint32_t rawAddr){ - Visit(rawAddr, false); + useCache(rawAddr, false); } void Cache::Write(uint32_t rawAddr){ - Visit(rawAddr, true); + useCache(rawAddr, true); } -void Cache::Visit(uint32_t rawAddr, bool isWrite){ +void Cache::useCache(uint32_t rawAddr, bool isWrite){ isWrite ? st.Write() : st.Read(); @@ -88,13 +88,13 @@ void Cache::Visit(uint32_t rawAddr, bool isWrite){ // Write to the L2 or Disk st.WriteBack(); if(NextCache!=nullptr) { - NextCache->Visit(p.UnParser(cl->tag, addr), true); + NextCache->useCache(p.UnParser(cl->tag, addr), true); } } if(NextCache!=nullptr){ // 2. Find it from Next Level - NextCache->Visit(rawAddr, false); + NextCache->useCache(rawAddr, false); } for(auto& b:(*s)) b.lru ++; @@ -137,7 +137,7 @@ void Cache::Visit(uint32_t rawAddr, bool isWrite){ if (!cl->v){ if(NextCache!=nullptr){ // 2. Find it from Next Level - NextCache->Visit(rawAddr, false); + NextCache->useCache(rawAddr, false); } // Empty Level 1 for(auto &b:(*s)) b.lru ++; @@ -162,7 +162,7 @@ void Cache::Visit(uint32_t rawAddr, bool isWrite){ if (vic->v && vic->d){ st.WriteBack(); if(NextCache!=nullptr) { - NextCache->Visit(p.UnParserVic(vic->tag, vaddr), true); + NextCache->useCache(p.UnParserVic(vic->tag, vaddr), true); } } } @@ -174,7 +174,7 @@ void Cache::Visit(uint32_t rawAddr, bool isWrite){ *cl = {addr.tag, 0, isWrite , true}; if(NextCache!=nullptr){ // 2. Find it from Next Level - NextCache->Visit(rawAddr, false); + NextCache->useCache(rawAddr, false); } } diff --git a/cache/TJU-2023-Computer-Organization/Proj1-2/Proj1-2/src/cache.h b/cache/TJU-2023-Computer-Organization/Proj1-2/Proj1-2/src/cache.h index c78c498..0330e36 100644 --- a/cache/TJU-2023-Computer-Organization/Proj1-2/Proj1-2/src/cache.h +++ b/cache/TJU-2023-Computer-Organization/Proj1-2/Proj1-2/src/cache.h @@ -49,7 +49,7 @@ public: void Write(uint32_t addr); void Read(uint32_t addr); - void Visit(uint32_t rawAddr, bool isWrite); + void useCache(uint32_t rawAddr, bool isWrite); friend ostream& operator<<(ostream& os, Cache& c){ if (!c.p.Size()) return os; diff --git a/cache/TJU-2023-Computer-Organization/Proj1-2/Proj1-2/src/simulator.h b/cache/TJU-2023-Computer-Organization/Proj1-2/Proj1-2/src/simulator.h index 06b5c28..7f7f3e6 100644 --- a/cache/TJU-2023-Computer-Organization/Proj1-2/Proj1-2/src/simulator.h +++ b/cache/TJU-2023-Computer-Organization/Proj1-2/Proj1-2/src/simulator.h @@ -36,7 +36,7 @@ public: char op; unsigned addr; while(getline(trace, line) && (istringstream(line) >> op >> hex >> addr)) { - c->Visit(addr, op == 'w'); + c->useCache(addr, op == 'w'); // cout << (*a); // cout << (*c); // if (m->Has2) cout << (*(c->NextCache));