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Author SHA1 Message Date
LYC 9f49b8b212 暂时跑通2 2024-10-29 21:44:38 +08:00
LYC 0b1d120fcd fix 1-1 2024-10-29 17:05:32 +08:00
36 changed files with 1760 additions and 75 deletions

18
.vscode/c_cpp_properties.json vendored Normal file
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@ -0,0 +1,18 @@
{
"configurations": [
{
"name": "windows-gcc-x64",
"includePath": [
"${workspaceFolder}/**"
],
"compilerPath": "gcc",
"cStandard": "${default}",
"cppStandard": "${default}",
"intelliSenseMode": "windows-gcc-x64",
"compilerArgs": [
""
]
}
],
"version": 4
}

24
.vscode/launch.json vendored Normal file
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@ -0,0 +1,24 @@
{
"version": "0.2.0",
"configurations": [
{
"name": "C/C++ Runner: Debug Session",
"type": "cppdbg",
"request": "launch",
"args": [],
"stopAtEntry": false,
"externalConsole": true,
"cwd": "d:/code/computer-organization/cache/Project1/Proj1-2/Proj1-2/src",
"program": "d:/code/computer-organization/cache/Project1/Proj1-2/Proj1-2/src/build/Debug/outDebug",
"MIMode": "gdb",
"miDebuggerPath": "gdb",
"setupCommands": [
{
"description": "Enable pretty-printing for gdb",
"text": "-enable-pretty-printing",
"ignoreFailures": true
}
]
}
]
}

120
.vscode/settings.json vendored
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@ -1,7 +1,117 @@
{
"files.associations": {
"iomanip": "cpp",
"iosfwd": "cpp",
"vector": "cpp"
}
"files.associations": {
"iomanip": "cpp",
"iosfwd": "cpp",
"vector": "cpp",
"iostream": "cpp",
"ostream": "cpp",
"algorithm": "cpp",
"ios": "cpp",
"atomic": "cpp",
"bit": "cpp",
"bitset": "cpp",
"cctype": "cpp",
"charconv": "cpp",
"clocale": "cpp",
"cmath": "cpp",
"compare": "cpp",
"concepts": "cpp",
"cstddef": "cpp",
"cstdint": "cpp",
"cstdio": "cpp",
"cstdlib": "cpp",
"cstring": "cpp",
"ctime": "cpp",
"cwchar": "cpp",
"exception": "cpp",
"format": "cpp",
"fstream": "cpp",
"initializer_list": "cpp",
"istream": "cpp",
"iterator": "cpp",
"limits": "cpp",
"locale": "cpp",
"memory": "cpp",
"new": "cpp",
"optional": "cpp",
"sstream": "cpp",
"stdexcept": "cpp",
"streambuf": "cpp",
"string": "cpp",
"system_error": "cpp",
"tuple": "cpp",
"type_traits": "cpp",
"typeinfo": "cpp",
"utility": "cpp",
"xfacet": "cpp",
"xiosbase": "cpp",
"xlocale": "cpp",
"xlocbuf": "cpp",
"xlocinfo": "cpp",
"xlocmes": "cpp",
"xlocmon": "cpp",
"xlocnum": "cpp",
"xloctime": "cpp",
"xmemory": "cpp",
"xstring": "cpp",
"xtr1common": "cpp",
"xutility": "cpp"
},
"C_Cpp_Runner.cCompilerPath": "gcc",
"C_Cpp_Runner.cppCompilerPath": "g++",
"C_Cpp_Runner.debuggerPath": "gdb",
"C_Cpp_Runner.cStandard": "",
"C_Cpp_Runner.cppStandard": "",
"C_Cpp_Runner.msvcBatchPath": "C:/Program Files/Microsoft Visual Studio/2022/Community/VC/Auxiliary/Build/vcvarsall.bat",
"C_Cpp_Runner.useMsvc": false,
"C_Cpp_Runner.warnings": [
"-Wall",
"-Wextra",
"-Wpedantic",
"-Wshadow",
"-Wformat=2",
"-Wcast-align",
"-Wconversion",
"-Wsign-conversion",
"-Wnull-dereference"
],
"C_Cpp_Runner.msvcWarnings": [
"/W4",
"/permissive-",
"/w14242",
"/w14287",
"/w14296",
"/w14311",
"/w14826",
"/w44062",
"/w44242",
"/w14905",
"/w14906",
"/w14263",
"/w44265",
"/w14928"
],
"C_Cpp_Runner.enableWarnings": true,
"C_Cpp_Runner.warningsAsError": false,
"C_Cpp_Runner.compilerArgs": [],
"C_Cpp_Runner.linkerArgs": [],
"C_Cpp_Runner.includePaths": [],
"C_Cpp_Runner.includeSearch": [
"*",
"**/*"
],
"C_Cpp_Runner.excludeSearch": [
"**/build",
"**/build/**",
"**/.*",
"**/.*/**",
"**/.vscode",
"**/.vscode/**"
],
"C_Cpp_Runner.useAddressSanitizer": false,
"C_Cpp_Runner.useUndefinedSanitizer": false,
"C_Cpp_Runner.useLeakSanitizer": false,
"C_Cpp_Runner.showCompilationTime": false,
"C_Cpp_Runner.useLinkTimeOptimization": false,
"C_Cpp_Runner.msvcSecureNoWarnings": false
}

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@ -0,0 +1,18 @@
{
"configurations": [
{
"name": "windows-gcc-x64",
"includePath": [
"${workspaceFolder}/**"
],
"compilerPath": "gcc",
"cStandard": "${default}",
"cppStandard": "${default}",
"intelliSenseMode": "windows-gcc-x64",
"compilerArgs": [
""
]
}
],
"version": 4
}

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@ -0,0 +1,24 @@
{
"version": "0.2.0",
"configurations": [
{
"name": "C/C++ Runner: Debug Session",
"type": "cppdbg",
"request": "launch",
"args": [],
"stopAtEntry": false,
"externalConsole": true,
"cwd": "d:/code/computer-organization/cache/Project1/Proj1-1/Proj1-1/src",
"program": "d:/code/computer-organization/cache/Project1/Proj1-1/Proj1-1/src/build/Debug/outDebug",
"MIMode": "gdb",
"miDebuggerPath": "gdb",
"setupCommands": [
{
"description": "Enable pretty-printing for gdb",
"text": "-enable-pretty-printing",
"ignoreFailures": true
}
]
}
]
}

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@ -0,0 +1,59 @@
{
"C_Cpp_Runner.cCompilerPath": "gcc",
"C_Cpp_Runner.cppCompilerPath": "g++",
"C_Cpp_Runner.debuggerPath": "gdb",
"C_Cpp_Runner.cStandard": "",
"C_Cpp_Runner.cppStandard": "",
"C_Cpp_Runner.msvcBatchPath": "C:/Program Files/Microsoft Visual Studio/2022/Community/VC/Auxiliary/Build/vcvarsall.bat",
"C_Cpp_Runner.useMsvc": false,
"C_Cpp_Runner.warnings": [
"-Wall",
"-Wextra",
"-Wpedantic",
"-Wshadow",
"-Wformat=2",
"-Wcast-align",
"-Wconversion",
"-Wsign-conversion",
"-Wnull-dereference"
],
"C_Cpp_Runner.msvcWarnings": [
"/W4",
"/permissive-",
"/w14242",
"/w14287",
"/w14296",
"/w14311",
"/w14826",
"/w44062",
"/w44242",
"/w14905",
"/w14906",
"/w14263",
"/w44265",
"/w14928"
],
"C_Cpp_Runner.enableWarnings": true,
"C_Cpp_Runner.warningsAsError": false,
"C_Cpp_Runner.compilerArgs": [],
"C_Cpp_Runner.linkerArgs": [],
"C_Cpp_Runner.includePaths": [],
"C_Cpp_Runner.includeSearch": [
"*",
"**/*"
],
"C_Cpp_Runner.excludeSearch": [
"**/build",
"**/build/**",
"**/.*",
"**/.*/**",
"**/.vscode",
"**/.vscode/**"
],
"C_Cpp_Runner.useAddressSanitizer": false,
"C_Cpp_Runner.useUndefinedSanitizer": false,
"C_Cpp_Runner.useLeakSanitizer": false,
"C_Cpp_Runner.showCompilationTime": false,
"C_Cpp_Runner.useLinkTimeOptimization": false,
"C_Cpp_Runner.msvcSecureNoWarnings": false
}

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@ -77,7 +77,7 @@ CacheTIO Cache::Address2TIO(uint32_t addr)
void Cache::useCache(uint32_t address, int method)
{
(method == WRITE)?this->StWrite():this->StRead();
(method == WRITE) ? this->StWrite() : this->StRead();
auto addr = this->Address2TIO(address);
auto set = &L1[addr.index];
@ -112,43 +112,86 @@ void Cache::useCache(uint32_t address, int method)
this->StReadMiss();
}
if (method == WRITE && this->writePolicy == WTNA)
if (method == WRITE && this->writePolicy == WTNA)
return;
auto toReplace = find_if(
set->block.begin(),
set->block.end(),
[](const Block& b){
[](const Block &b)
{
return !b.valid;
}
);
});
if (toReplace == set->block.end()){
if (toReplace == set->block.end())
{
// Replace
toReplace = min_element(
set->block.begin(),
set->block.end(),
this->replicementPolicy == LRU
?
[](const Block &a, const Block &b){ return a.lastUsed < b.lastUsed; }
:
[](const Block&a, const Block&b){ return a.countBlock < b.countBlock; }
);
set->block.begin(),
set->block.end(),
this->replicementPolicy == LRU
? [](const Block &a, const Block &b)
{ return a.lastUsed < b.lastUsed; }
: [](const Block &a, const Block &b)
{ return a.countBlock < b.countBlock; });
}
if (toReplace->dirty) {
if (toReplace->dirty)
{
// Write to the L2 or Disk
this->StWriteBack();
}
set->countSet = toReplace->countBlock;
*toReplace = {addr.tag, set->countSet + 1, lru ++, (bool)method, true};
*toReplace = {addr.tag, set->countSet + 1, lru++, (bool)method, true};
return;
}
double Cache::GetHT()
{
return 0.25 + 2.5 * (size / (512.0 * 1024)) + 0.025 * (blockSize / 16.0) + 0.025 * assoc;
}
void Cache::printResult(){
return ;
double Cache::GetMP()
{
return 20 + 0.5 * (blockSize / 16.0);
}
void Cache::printCache(string filename)
{
cout << " ===== Simulator configuration =====\n";
cout << " L1_BLOCKSIZE:" << setw(22) << this->blockSize << endl;
cout << " L1_SIZE:" << setw(27) << this->size << endl;
cout << " L1_ASSOC:" << setw(26) << this->assoc << endl;
cout << " L1_REPLACEMENT_POLICY:" << setw(13) << this->replicementPolicy << endl;
cout << " L1_WRITE_POLICY:" << setw(19) << this->writePolicy << endl;
cout << " trace_file:" << setw(24) << filename << endl;
cout << " ===================================\n\n";
cout << "===== L1 contents =====" << endl;
for (uint32_t i = 0; i != this->L1.size(); i++)
{
cout << "set" << setw(4) << i << ":";
for (auto &b : this->L1[i].block)
cout << hex << setw(8) << b.tag << ' ' << ((this->writePolicy == WBWA && b.dirty) ? 'D' : ' ');
cout << endl
<< dec;
}
cout << "\n ====== Simulation results (raw) ======\n";
cout << " a. number of L1 reads:" << setw(16) << this->readCount << endl;
cout << " b. number of L1 read misses:" << setw(10) << this->readMiss << endl;
cout << " c. number of L1 writes:" << setw(15) << this->writeCount << endl;
cout << " d. number of L1 write misses:" << setw(9) << this->writeMiss << endl;
double mr = (this->readMiss + this->writeMiss) / (double)(this->readCount + this->writeCount);
cout << " e. L1 miss rate:" << setw(22) << fixed << setprecision(4) << mr << endl;
cout << " f. number of writebacks from L1:" << setw(6) << this->writeBack << endl;
cout << " g. total memory traffic:" << setw(14) << ((this->writePolicy) ? (this->readMiss + this->writeCount) : (this->readMiss + this->writeMiss + this->writeBack));
cout << "\n\n ==== Simulation results (performance) ====\n";
double ht = this->GetHT();
double mp = this->GetMP();
cout << " 1. average access time:" << setw(15) << ht + mr * mp << " ns";
// return cout;
}

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@ -20,10 +20,10 @@ struct Block
bool dirty = false; // dirty
bool valid = false; // valid
bool operator<(const Block &t) { return this->countBlock < t.countBlock; }
friend ostream &operator<<(ostream &os, Block &b)
friend ostream &operator<<(ostream &cout, Block &b)
{
os << "{tag:" << b.tag << ", Count-Block:" << b.countBlock << ", Last-Used:" << b.lastUsed << ", Dirty:" << b.dirty << ", Valid:" << b.valid << "}";
return os;
cout << "{tag:" << b.tag << ", Count-Block:" << b.countBlock << ", Last-Used:" << b.lastUsed << ", Dirty:" << b.dirty << ", Valid:" << b.valid << "}";
return cout;
}
};
@ -78,57 +78,13 @@ public:
void StReadMiss();
void StWriteBack();
void writeCache(uint32_t address);
void readCache(uint32_t address);
void useCache(uint32_t address, int method);
void printResult();
double GetHT() {
return 0.25 + 2.5 * (size/ (512.0 * 1024)) + 0.025 * (blockSize/ 16.0) + 0.025 * assoc;
}
double GetHT();
double GetMP();
double GetMP() {
return 20 + 0.5 * (blockSize / 16.0);
}
void printCache(ostream& os, Cache c,string filename){
os << " ===== Simulator configuration =====\n";
os << " L1_BLOCKSIZE:" << setw(22) << c.blockSize << endl;
os << " L1_SIZE:" << setw(27) << c.size << endl;
os << " L1_ASSOC:" << setw(26) << c.assoc << endl;
os << " L1_REPLACEMENT_POLICY:" << setw(13) << c.replicementPolicy << endl;
os << " L1_WRITE_POLICY:" << setw(19) << c.writePolicy << endl;
os << " trace_file:" << setw(24) << filename << endl;
os << " ===================================\n\n";
os << "===== L1 contents =====" << endl;
for (uint32_t i=0;i!=c.L1.size();i++){
os << "set" << setw(4) << i << ":";
for(auto &b:c.L1[i].block)
os << hex << setw(8) << b.tag << ' ' << ((c.writePolicy == WBWA && b.dirty) ? 'D' : ' ');
os << endl << dec;
}
os << "\n ====== Simulation results (raw) ======\n";
os << " a. number of L1 reads:" << setw(16) << c.readCount << endl;
os << " b. number of L1 read misses:" << setw(10) << c.readMiss << endl;
os << " c. number of L1 writes:" << setw(15) << c.writeCount << endl;
os << " d. number of L1 write misses:" << setw(9) << c.writeMiss << endl;
double mr = (c.readMiss + c.writeMiss) / (double)(c.readCount + c.writeCount);
os << " e. L1 miss rate:" << setw(22) << fixed << setprecision(4) << mr << endl;
os << " f. number of writebacks from L1:" << setw(6) << c.writeBack << endl;
os << " g. total memory traffic:" << setw(14) << ((c.writePolicy) ? (c.readMiss + c.writeCount) : (c.readMiss + c.writeMiss + c.writeBack));
os << "\n\n ==== Simulation results (performance) ====\n";
double ht = c.GetHT();
double mp = c.GetMP();
os << " 1. average access time:" << setw(15) << ht + mr * mp << " ns";
//return os;
}
void printCache(string filename);
CacheTIO Address2TIO(uint32_t addr);
};

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@ -29,7 +29,7 @@ int main(int argc, char *argv[])
cache->useCache(addr, op == 'w');
}
trace.close();
cache->printCache(cout, *cache, fileName);
cache->printCache(fileName);
}
catch (const char *e)
{

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@ -0,0 +1,18 @@
{
"configurations": [
{
"name": "windows-gcc-x64",
"includePath": [
"${workspaceFolder}/**"
],
"compilerPath": "gcc",
"cStandard": "${default}",
"cppStandard": "${default}",
"intelliSenseMode": "windows-gcc-x64",
"compilerArgs": [
""
]
}
],
"version": 4
}

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@ -0,0 +1,24 @@
{
"version": "0.2.0",
"configurations": [
{
"name": "C/C++ Runner: Debug Session",
"type": "cppdbg",
"request": "launch",
"args": [],
"stopAtEntry": false,
"externalConsole": true,
"cwd": "d:/code/computer-organization/cache/Project1/Proj1-2/Proj1-2/src",
"program": "d:/code/computer-organization/cache/Project1/Proj1-2/Proj1-2/src/build/Debug/outDebug",
"MIMode": "gdb",
"miDebuggerPath": "gdb",
"setupCommands": [
{
"description": "Enable pretty-printing for gdb",
"text": "-enable-pretty-printing",
"ignoreFailures": true
}
]
}
]
}

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@ -0,0 +1,68 @@
{
"C_Cpp_Runner.cCompilerPath": "gcc",
"C_Cpp_Runner.cppCompilerPath": "g++",
"C_Cpp_Runner.debuggerPath": "gdb",
"C_Cpp_Runner.cStandard": "",
"C_Cpp_Runner.cppStandard": "",
"C_Cpp_Runner.msvcBatchPath": "C:/Program Files/Microsoft Visual Studio/2022/Community/VC/Auxiliary/Build/vcvarsall.bat",
"C_Cpp_Runner.useMsvc": false,
"C_Cpp_Runner.warnings": [
"-Wall",
"-Wextra",
"-Wpedantic",
"-Wshadow",
"-Wformat=2",
"-Wcast-align",
"-Wconversion",
"-Wsign-conversion",
"-Wnull-dereference"
],
"C_Cpp_Runner.msvcWarnings": [
"/W4",
"/permissive-",
"/w14242",
"/w14287",
"/w14296",
"/w14311",
"/w14826",
"/w44062",
"/w44242",
"/w14905",
"/w14906",
"/w14263",
"/w44265",
"/w14928"
],
"C_Cpp_Runner.enableWarnings": true,
"C_Cpp_Runner.warningsAsError": false,
"C_Cpp_Runner.compilerArgs": [],
"C_Cpp_Runner.linkerArgs": [],
"C_Cpp_Runner.includePaths": [],
"C_Cpp_Runner.includeSearch": [
"*",
"**/*"
],
"C_Cpp_Runner.excludeSearch": [
"**/build",
"**/build/**",
"**/.*",
"**/.*/**",
"**/.vscode",
"**/.vscode/**"
],
"C_Cpp_Runner.useAddressSanitizer": false,
"C_Cpp_Runner.useUndefinedSanitizer": false,
"C_Cpp_Runner.useLeakSanitizer": false,
"C_Cpp_Runner.showCompilationTime": false,
"C_Cpp_Runner.useLinkTimeOptimization": false,
"C_Cpp_Runner.msvcSecureNoWarnings": false,
"files.associations": {
"fstream": "cpp",
"iostream": "cpp",
"sstream": "cpp",
"vector": "cpp",
"ostream": "cpp",
"iosfwd": "cpp",
"iomanip": "cpp"
}
}

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@ -0,0 +1,60 @@
===== Simulator configuration =====
BLOCKSIZE: 32
L1_SIZE: 2048
L1_ASSOC: 4
Victim_Cache_SIZE: 0
L2_SIZE: 4096
L2_ASSOC: 8
trace_file: gcc_trace.txt
===================================
===== L1 contents =====
set 0: 20028d D 20018a 20028e D 200198 D
set 1: 2001c1 D 20028d D 200153 D 20013b
set 2: 200223 D 20028d D 200241 2001c1
set 3: 20018a 2001ac D 20028e D 20028d D
set 4: 20018f D 2000f9 20017a D 20018a
set 5: 200009 20017a 2000fa 20018a
set 6: 200009 2000f9 20028d D 20018a
set 7: 200009 2001ac 2000fa 200149
set 8: 200009 3d819c D 20017b D 2000f9
set 9: 200009 2000fa 2000f9 2001b2 D
set 10: 200009 200214 2000fa 20023f
set 11: 200009 2001ab 20013a 20023f
set 12: 20018f D 2001f2 2001aa 20018a D
set 13: 20028d D 20018d D 20013a 20028c D
set 14: 20013a 20018d D 20028d D 2001ad D
set 15: 2001f8 D 20028c D 20013a 20018d D
===== L2 contents =====
set 0: 20018a 20028e 200198 2001ab 2001d1 D 20017a D 20028d 2001f4 D
set 1: 2001c1 200153 D 20028e D 20013b 200198 D 2000fb 2001d1 D 20028d
set 2: 200241 20028d D 200223 200149 200198 D 20018a 2001c1 D 20013b
set 3: 2001ac 2001c1 D 20028e 2001b0 D 20028d 20028c D 20018a 2001bd D
set 4: 2000f9 20028e D 20018a 20028d D 20017a D 20023f 200149 2002b1 D
set 5: 20017a 20028e D 200009 20028d D 2000fa 2001b2 D 20018a 20023f
set 6: 200009 2000f9 2001b2 D 20023f 2001ac D 2001ad D 20028d 20028c D
set 7: 200009 20028d D 2000fa 2001b2 D 2001ac 20023f 200149 2001f6 D
set 8: 200009 20017b D 2000fa 2001b2 D 2000f9 20028d D 20023f 200149
set 9: 200009 2000fa 20028d D 2001b2 20023f 3d819c D 20028c D 2001aa
set 10: 200009 200214 D 20028d D 20023f 2001ab D 2001aa 2001fc D 2000fa
set 11: 200009 2001ab 20028d D 20023f 2001aa 200214 D 20028c D 20013a
set 12: 20018f 2001aa 20018a 2001f2 20023f 20028d D 20018d D 2001ab
set 13: 20028d 2001b3 D 20018d 2001ab D 20013a 2001b2 D 20028c 2001fe D
set 14: 20028d 20028c D 20018d 2001a7 D 20013a 2001b2 D 2001ad D 2001fd D
set 15: 20013a 20028d D 20018d 200197 D 2001f8 2001a9 D 200222 D 2001d1 D
====== Simulation results (raw) ======
a. number of L1 reads: 63640
b. number of L1 read misses: 5170
c. number of L1 writes: 36360
d. number of L1 write misses: 4452
e. L1 miss rate: 0.0962
f. number of swaps: 0
g. number of victim cache writeback: 0
h. number of L2 reads: 9622
i. number of L2 read misses: 5313
j. number of L2 writes: 4942
k. number of L2 write misses: 151
l. L2 miss rate: 0.5522
m. number of L2 writebacks: 2978
n. total memory traffic: 8442
==== Simulation results (performance) ====
1. average access time: 1.7920 ns

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@ -0,0 +1,164 @@
===== Simulator configuration =====
BLOCKSIZE: 16
L1_SIZE: 1024
L1_ASSOC: 8
Victim_Cache_SIZE: 0
L2_SIZE: 8192
L2_ASSOC: 4
trace_file: go_trace.txt
===================================
===== L1 contents =====
set 0: 800470 D 80046f D 80046e D 80046d D 80046c D 80046b D 80046a D 800469 D
set 1: 800470 D 80046f D 80046e D 80046d D 80046c D 80046b D 80046a D 800469 D
set 2: 800470 D 80046f D 80046e D 80046d D 80046c D 80046b D 80046a D 800469 D
set 3: 800470 D 80046f D 80046e D 80046d D 80046c D 80046b D 80046a D 800469 D
set 4: 800470 D 80046f D 80046e D 80046d D 80046c D 80046b D 80046a D 800469 D
set 5: 80046f D 80046e D 80046d D 80046c D 80046b D 80046a D 800469 D 800468 D
set 6: 80046f D 80046e D 80046d D 80046c D 80046b D 80046a D 800469 D 800468 D
set 7: 80046f D 80046e D 80046d D 80046c D 80046b D 80046a D 800469 D 800468 D
===== L2 contents =====
set 0: 80047 80046 D 80045 D 80044 D
set 1: 80047 80046 D 80045 D 80044 D
set 2: 80047 80046 D 80045 D 80044 D
set 3: 80047 80046 D 80045 D 80044 D
set 4: 80047 80046 D 80045 D 80044 D
set 5: 80046 D 80045 D 80044 D 80043 D
set 6: 80046 D 80045 D 80044 D 80043 D
set 7: 80046 D 80045 D 80044 D 80043 D
set 8: 80046 D 80045 D 80044 D 80043 D
set 9: 80046 D 80045 D 80044 D 80043 D
set 10: 80046 D 80045 D 80044 D 80043 D
set 11: 80046 D 80045 D 80044 D 80043 D
set 12: 80046 D 80045 D 80044 D 80043 D
set 13: 80046 D 80045 D 80044 D 80043 D
set 14: 80046 D 80045 D 80044 D 80043 D
set 15: 80046 D 80045 D 80044 D 80043 D
set 16: 80046 D 80045 D 80044 D 80043 D
set 17: 80046 D 80045 D 80044 D 80043 D
set 18: 80046 D 80045 D 80044 D 80043 D
set 19: 80046 D 80045 D 80044 D 80043 D
set 20: 80046 D 80045 D 80044 D 80043 D
set 21: 80046 D 80045 D 80044 D 80043 D
set 22: 80046 D 80045 D 80044 D 80043 D
set 23: 80046 D 80045 D 80044 D 80043 D
set 24: 80046 D 80045 D 80044 D 80043 D
set 25: 80046 D 80045 D 80044 D 80043 D
set 26: 80046 D 80045 D 80044 D 80043 D
set 27: 80046 D 80045 D 80044 D 80043 D
set 28: 80046 D 80045 D 80044 D 80043 D
set 29: 80046 D 80045 D 80044 D 80043 D
set 30: 80046 D 80045 D 80044 D 80043 D
set 31: 80046 D 80045 D 80044 D 80043 D
set 32: 80046 D 80045 D 80044 D 80043 D
set 33: 80046 D 80045 D 80044 D 80043 D
set 34: 80046 D 80045 D 80044 D 80043 D
set 35: 80046 D 80045 D 80044 D 80043 D
set 36: 80046 D 80045 D 80044 D 80043 D
set 37: 80046 D 80045 D 80044 D 80043 D
set 38: 80046 D 80045 D 80044 D 80043 D
set 39: 80046 D 80045 D 80044 D 80043 D
set 40: 80046 D 80045 D 80044 D 80043 D
set 41: 80046 D 80045 D 80044 D 80043 D
set 42: 80046 D 80045 D 80044 D 80043 D
set 43: 80046 D 80045 D 80044 D 80043 D
set 44: 80046 D 80045 D 80044 D 80043 D
set 45: 80046 D 80045 D 80044 D 80043 D
set 46: 80046 D 80045 D 80044 D 80043 D
set 47: 80046 D 80045 D 80044 D 80043 D
set 48: 80046 D 80045 D 80044 D 80043 D
set 49: 80046 D 80045 D 80044 D 80043 D
set 50: 80046 D 80045 D 80044 D 80043 D
set 51: 80046 D 80045 D 80044 D 80043 D
set 52: 80046 D 80045 D 80044 D 80043 D
set 53: 80046 D 80045 D 80044 D 80043 D
set 54: 80046 D 80045 D 80044 D 80043 D
set 55: 80046 D 80045 D 80044 D 80043 D
set 56: 80046 D 80045 D 80044 D 80043 D
set 57: 80046 D 80045 D 80044 D 80043 D
set 58: 80046 D 80045 D 80044 D 80043 D
set 59: 80046 D 80045 D 80044 D 80043 D
set 60: 80046 D 80045 D 80044 D 80043 D
set 61: 80046 D 80045 D 80044 D 80043 D
set 62: 80046 D 80045 D 80044 D 80043 D
set 63: 80046 D 80045 D 80044 D 80043 D
set 64: 80046 D 80045 D 80044 D 80043 D
set 65: 80046 D 80045 D 80044 D 80043 D
set 66: 80046 D 80045 D 80044 D 80043 D
set 67: 80046 D 80045 D 80044 D 80043 D
set 68: 80046 D 80045 D 80044 D 80043 D
set 69: 80046 80045 D 80044 D 80043 D
set 70: 80046 80045 D 80044 D 80043 D
set 71: 80046 80045 D 80044 D 80043 D
set 72: 80046 80045 D 80044 D 80043 D
set 73: 80046 80045 D 80044 D 80043 D
set 74: 80046 80045 D 80044 D 80043 D
set 75: 80046 80045 D 80044 D 80043 D
set 76: 80046 80045 D 80044 D 80043 D
set 77: 80046 80045 D 80044 D 80043 D
set 78: 80046 80045 D 80044 D 80043 D
set 79: 80046 80045 D 80044 D 80043 D
set 80: 80046 80045 D 80044 D 80043 D
set 81: 80046 80045 D 80044 D 80043 D
set 82: 80046 80045 D 80044 D 80043 D
set 83: 80046 80045 D 80044 D 80043 D
set 84: 80046 80045 D 80044 D 80043 D
set 85: 80046 80045 D 80044 D 80043 D
set 86: 80046 80045 D 80044 D 80043 D
set 87: 80046 80045 D 80044 D 80043 D
set 88: 80046 80045 D 80044 D 80043 D
set 89: 80046 80045 D 80044 D 80043 D
set 90: 80046 80045 D 80044 D 80043 D
set 91: 80046 80045 D 80044 D 80043 D
set 92: 80046 80045 D 80044 D 80043 D
set 93: 80046 80045 D 80044 D 80043 D
set 94: 80046 80045 D 80044 D 80043 D
set 95: 80046 80045 D 80044 D 80043 D
set 96: 80046 80045 D 80044 D 80043 D
set 97: 80046 80045 D 80044 D 80043 D
set 98: 80046 80045 D 80044 D 80043 D
set 99: 80046 80045 D 80044 D 80043 D
set 100: 80046 80045 D 80044 D 80043 D
set 101: 80046 80045 D 80044 D 80043 D
set 102: 80046 80045 D 80044 D 80043 D
set 103: 80046 80045 D 80044 D 80043 D
set 104: 80046 80045 D 80044 D 80043 D
set 105: 80046 80045 D 80044 D 80043 D
set 106: 80046 80045 D 80044 D 80043 D
set 107: 80046 80045 D 80044 D 80043 D
set 108: 80046 80045 D 80044 D 80043 D
set 109: 80046 80045 D 80044 D 80043 D
set 110: 80046 80045 D 80044 D 80043 D
set 111: 80046 80045 D 80044 D 80043 D
set 112: 80046 80045 D 80044 D 80043 D
set 113: 80046 80045 D 80044 D 80043 D
set 114: 80046 80045 D 80044 D 80043 D
set 115: 80046 80045 D 80044 D 80043 D
set 116: 80046 80045 D 80044 D 80043 D
set 117: 80046 80045 D 80044 D 80043 D
set 118: 80046 80045 D 80044 D 80043 D
set 119: 80046 80045 D 80044 D 80043 D
set 120: 80046 80045 D 80044 D 80043 D
set 121: 80046 80045 D 80044 D 80043 D
set 122: 80046 80045 D 80044 D 80043 D
set 123: 80046 80045 D 80044 D 80043 D
set 124: 80046 80045 D 80044 D 80043 D
set 125: 80046 80045 D 80044 D 80043 D
set 126: 80046 80045 D 80044 D 80043 D
set 127: 80046 80045 D 80044 D 80043 D
====== Simulation results (raw) ======
a. number of L1 reads: 60613
b. number of L1 read misses: 3819
c. number of L1 writes: 39387
d. number of L1 write misses: 6341
e. L1 miss rate: 0.1016
f. number of swaps: 0
g. number of victim cache writeback: 0
h. number of L2 reads: 10160
i. number of L2 read misses: 9847
j. number of L2 writes: 8323
k. number of L2 write misses: 3
l. L2 miss rate: 0.9692
m. number of L2 writebacks: 7869
n. total memory traffic: 17719
==== Simulation results (performance) ====
1. average access time: 2.7692 ns

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===== Simulator configuration =====
BLOCKSIZE: 32
L1_SIZE: 1024
L1_ASSOC: 8
Victim_Cache_SIZE: 256
L2_SIZE: 0
L2_ASSOC: 0
trace_file: perl_trace.txt
===================================
===== L1 contents =====
set 0: 8003d7 80037c D 800276 D 8003d8 800379 800368 f6067b D 8003d9
set 1: 80056c 800045 80058c 8003d7 8002c1 D 800379 8003d8 80037b
set 2: 800045 80058c D 8003d2 800379 D f6067d D 80018e 8003d8 f60677
set 3: 800580 8003d1 f6067d D 800325 80018e 8003d8 8003d2 D 800276
===== Victim Cache contents =====
set 0: 2000f4f 3d819ed D 20006a2 D 20009da 3d819dd 20006a1 20006a5 D 2000f4c D
====== Simulation results (raw) ======
a. number of L1 reads: 70107
b. number of L1 read misses: 14002
c. number of L1 writes: 29893
d. number of L1 write misses: 4835
e. L1 miss rate: 0.1884
f. number of swaps: 4060
g. number of victim cache writeback: 6735
h. number of L2 reads: 0
i. number of L2 read misses: 0
j. number of L2 writes: 0
k. number of L2 write misses: 0
l. L2 miss rate: 0
m. number of L2 writebacks: 0
n. total memory traffic: 25572
==== Simulation results (performance) ====
1. average access time: 4.4607 ns

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===== Simulator configuration =====
BLOCKSIZE: 128
L1_SIZE: 1024
L1_ASSOC: 2
Victim_Cache_SIZE: 1024
L2_SIZE: 4096
L2_ASSOC: 4
trace_file: gcc_trace.txt
===================================
===== L1 contents =====
set 0: 2001c1 D 20028d D
set 1: 200009 20017a
set 2: 200009 200214
set 3: 2001f8 D 20028c D
===== Victim Cache contents =====
set 0: f60672 D 80063d D 80088c D 800904 8006b1 800628 8006ae 80063f D
===== L2 contents =====
set 0: 1000c5 1000d6 D 100147 D 1000cc D
set 1: 1000bd D 100147 D 10007d 1000d6
set 2: 10010a 1000d9 D 10009d 10007d
set 3: 1000fc D 1000c5 D 1000d5 10009d
set 4: 1000a9 D 100120 100111 100146 D
set 5: 100004 10007c 1000c7 D 100146 D
set 6: 100004 1000bd D 1000d5 10007c
set 7: 1000c7 1000d5 1000c6 D 10011f
====== Simulation results (raw) ======
a. number of L1 reads: 63640
b. number of L1 read misses: 8160
c. number of L1 writes: 36360
d. number of L1 write misses: 3824
e. L1 miss rate: 0.1198
f. number of swaps: 9722
g. number of victim cache writeback: 4763
h. number of L2 reads: 11984
i. number of L2 read misses: 7690
j. number of L2 writes: 4763
k. number of L2 write misses: 1205
l. L2 miss rate: 0.6417
m. number of L2 writebacks: 3198
n. total memory traffic: 12093
==== Simulation results (performance) ====
1. average access time: 2.6884 ns

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===== Simulator configuration =====
BLOCKSIZE: 64
L1_SIZE: 8192
L1_ASSOC: 2
Victim_Cache_SIZE: 1024
L2_SIZE: 16384
L2_ASSOC: 4
trace_file: perl_trace.txt
===================================
===== L1 contents =====
set 0: 4002d D 4002c D
set 1: 4002c D 4002d D
set 2: 40016 D 4002d D
set 3: 4002d D 4002c D
set 4: 4002d D 4001d D
set 5: 4002a 4002c D
set 6: 4002b D 4002c D
set 7: 4001d 4002c D
set 8: 4000f D 4002c D
set 9: 40011 D 4002c D
set 10: 40002 4002c D
set 11: 40002 40019
set 12: 4002c D 40028
set 13: 40013 D 4002b
set 14: 40013 D 4002c
set 15: 4001d 40028
set 16: 4001b 4000d
set 17: 4000d D 4002b
set 18: 4000d D 40028
set 19: 4001e 4000d
set 20: 4001e 40028
set 21: 4002b D 4002a
set 22: 4000d 4002a
set 23: 4002b D 4002c D
set 24: 4002b D 4002c D
set 25: 4002c D 4002b D
set 26: 4002b D 4002c D
set 27: 4002b D 4002c D
set 28: 4002c D 4002b D
set 29: 4000c 4002c D
set 30: 4002c D 4002b D
set 31: 4002c D 4002b D
set 32: 4001e D 4002c D
set 33: 4002c D 4002b D
set 34: 4001e 4001c D
set 35: 4001e 4002c D
set 36: 4001e 4002c D
set 37: 4001e D 4000b D
set 38: 4001e D 4002c D
set 39: 4001e D 4002c D
set 40: 4002c D 4002b D
set 41: 4002c D 4002b D
set 42: 4001e 4002a
set 43: 40016 D 4001e
set 44: 40013 D 4002c D
set 45: 40013 4002c D
set 46: 4001e D 7b033 D
set 47: 7b033 4002c D
set 48: 4001e 4001c
set 49: 4001e 4002c D
set 50: 4001b D 4001e
set 51: 4001b D 4002c D
set 52: 4001b D 4001e
set 53: 4002c D 4001d D
set 54: 4001b 7b033 D
set 55: 4002c D 4002b D
set 56: 4001b D 4002b
set 57: 7b033 D 4002c D
set 58: 4002c D 4002b D
set 59: 7b033 D 4002c D
set 60: 4002c D 4002b D
set 61: 7b033 D 4002c D
set 62: 4002c D 40029 D
set 63: 4002c D 4001d
===== Victim Cache contents =====
set 0: 10004ee D 1000ad4 D 1000b04 D 1000ac3 D 1000774 1000b02 D 1000ac1 D 1000b38 D 1000ac0 D 1000a13 1000aff D 1000afe D 1000b25 1000a7d 1000abc 1000750
===== L2 contents =====
set 0: 4002d 4002c 4002a D 4002b D
set 1: 4002d 4002a D 4002c 4002b
set 2: 4002d 4002c 4002a D 4001d D
set 3: 4002d 4002a D 4002c 4002b
set 4: 4002d 4002c 4002b D 4001d D
set 5: 4002b D 4002a D 4002c 4001d D
set 6: 4001d D 4002c 4002a D 4002b
set 7: 4002a D 4002c 4002b D 4001d D
set 8: 4002b D 4002c 4002a D 40028
set 9: 4002c 4002a D 4001d D 40011 D
set 10: 4002c 4002b D 40002 40028
set 11: 4002a 4002c D 4001d D 40028
set 12: 4002b D 4002c 40028 4002a D
set 13: 4002c D 4002b 4002a D 40028
set 14: 4002c D 4002a D 40028 40013 D
set 15: 4002c D 4001d 4002a D 40028
set 16: 4001d 4002c D 40028 4002a D
set 17: 4002b D 4002c D 40028 4000d D
set 18: 4002b D 4002c D 40028 4002a D
set 19: 40028 4002b D 4002c D 4000d
set 20: 40028 4002c D 4002b D 4001d D
set 21: 4002c D 4002a D 4001d D 4002b
set 22: 4002b D 4002a 4002c D 4000d D
set 23: 4002a D 4002c 4001d D 4002b
set 24: 4001d D 4002c 4002a D 4002b
set 25: 4002a D 4002c 4001d D 4002b
set 26: 4001d D 4002c 4002a D 4002b
set 27: 4001d D 4002b D 4002c 4002a D
set 28: 4002a D 4002c 4001d D 4002b
set 29: 4002c 4002b D 4001d D 4002a D
set 30: 4002a D 4002c 4001d D 4002b
set 31: 4002a D 4002c 4001d D 4002b
set 32: 4002b D 4002c 4001e D 4002a D
set 33: 4002a D 4002c 4001d D 4002b
set 34: 4002c D 4002b D 4001d D 4001c D
set 35: 4002b D 4002c 4002a D 4001d D
set 36: 4002b D 4002c 4002a D 4001d D
set 37: 4002c D 4002b D 4001c 4001e D
set 38: 4002c 4002b D 4002a D 4001d D
set 39: 4002b D 4002c 4001c D 4002a D
set 40: 4002c 4001c D 4002a D 4002b
set 41: 4002a D 4002c 4001d D 4002b
set 42: 4002c D 4002a D 4002b D 4001d
set 43: 4002c D 4002a 4002b D 4001d D
set 44: 4002b D 4002c 40013 D 4002a D
set 45: 4002b D 4002c 4001c D 40013
set 46: 4002c D 4002b D 40013 D 4002a D
set 47: 4002b D 4002c 4001c D 7b033 D
set 48: 4002c D 4002b D 4001c 4002a D
set 49: 4001c D 4002c 4002b D 4001d D
set 50: 4002c D 4002b D 4001d D 4002a D
set 51: 4002b D 4002c 4001d D 4002a D
set 52: 4001d D 4002c D 4002b D 4001c D
set 53: 4002b D 4002c 4002a D 4001c D
set 54: 4002c D 4002b D 4001d D 4002a D
set 55: 4001c D 4002c 4001d D 4002b
set 56: 4002b D 4002c 4001d D 4001b D
set 57: 4002c 4002b D 4002a D 4001c D
set 58: 4001d D 4002c 4002a D 4002b
set 59: 4002c 4002b D 4002a D 4001d D
set 60: 4002c 4002a D 4002b 4001d D
set 61: 4002c 4002b D 40029 D 4001d D
set 62: 4002c 4002a D 4002b 4001d D
set 63: 4002c 4001c D 4002b 4002a D
====== Simulation results (raw) ======
a. number of L1 reads: 70107
b. number of L1 read misses: 1927
c. number of L1 writes: 29893
d. number of L1 write misses: 569
e. L1 miss rate: 0.0250
f. number of swaps: 1382
g. number of victim cache writeback: 766
h. number of L2 reads: 2496
i. number of L2 read misses: 1268
j. number of L2 writes: 766
k. number of L2 write misses: 123
l. L2 miss rate: 0.5080
m. number of L2 writebacks: 415
n. total memory traffic: 1806
==== Simulation results (performance) ====
1. average access time: 0.7874 ns

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{
"configurations": [
{
"name": "windows-gcc-x64",
"includePath": [
"${workspaceFolder}/**"
],
"compilerPath": "gcc",
"cStandard": "${default}",
"cppStandard": "${default}",
"intelliSenseMode": "windows-gcc-x64",
"compilerArgs": [
""
]
}
],
"version": 4
}

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{
"version": "0.2.0",
"configurations": [
{
"name": "C/C++ Runner: Debug Session",
"type": "cppdbg",
"request": "launch",
"args": [],
"stopAtEntry": false,
"externalConsole": true,
"cwd": "d:/code/computer-organization/cache/Project1/Proj1-2/Proj1-2/src",
"program": "d:/code/computer-organization/cache/Project1/Proj1-2/Proj1-2/src/build/Debug/outDebug",
"MIMode": "gdb",
"miDebuggerPath": "gdb",
"setupCommands": [
{
"description": "Enable pretty-printing for gdb",
"text": "-enable-pretty-printing",
"ignoreFailures": true
}
]
}
]
}

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@ -0,0 +1,69 @@
{
"C_Cpp_Runner.cCompilerPath": "gcc",
"C_Cpp_Runner.cppCompilerPath": "g++",
"C_Cpp_Runner.debuggerPath": "gdb",
"C_Cpp_Runner.cStandard": "",
"C_Cpp_Runner.cppStandard": "",
"C_Cpp_Runner.msvcBatchPath": "C:/Program Files/Microsoft Visual Studio/2022/Community/VC/Auxiliary/Build/vcvarsall.bat",
"C_Cpp_Runner.useMsvc": false,
"C_Cpp_Runner.warnings": [
"-Wall",
"-Wextra",
"-Wpedantic",
"-Wshadow",
"-Wformat=2",
"-Wcast-align",
"-Wconversion",
"-Wsign-conversion",
"-Wnull-dereference"
],
"C_Cpp_Runner.msvcWarnings": [
"/W4",
"/permissive-",
"/w14242",
"/w14287",
"/w14296",
"/w14311",
"/w14826",
"/w44062",
"/w44242",
"/w14905",
"/w14906",
"/w14263",
"/w44265",
"/w14928"
],
"C_Cpp_Runner.enableWarnings": true,
"C_Cpp_Runner.warningsAsError": false,
"C_Cpp_Runner.compilerArgs": [],
"C_Cpp_Runner.linkerArgs": [],
"C_Cpp_Runner.includePaths": [],
"C_Cpp_Runner.includeSearch": [
"*",
"**/*"
],
"C_Cpp_Runner.excludeSearch": [
"**/build",
"**/build/**",
"**/.*",
"**/.*/**",
"**/.vscode",
"**/.vscode/**"
],
"C_Cpp_Runner.useAddressSanitizer": false,
"C_Cpp_Runner.useUndefinedSanitizer": false,
"C_Cpp_Runner.useLeakSanitizer": false,
"C_Cpp_Runner.showCompilationTime": false,
"C_Cpp_Runner.useLinkTimeOptimization": false,
"C_Cpp_Runner.msvcSecureNoWarnings": false,
"files.associations": {
"fstream": "cpp",
"iomanip": "cpp",
"iostream": "cpp",
"xstring": "cpp",
"iosfwd": "cpp",
"string": "cpp",
"exception": "cpp",
"vector": "cpp"
}
}

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CC = g++
#OPT = -O3 -m32
OPT = -g
WARN = -Wall
CFLAGS = $(OPT) $(WARN) $(INC) $(LIB)
# List all your .cc files here (source files, excluding header files)
SIM_SRC = main.cc cache.cc NewCache.cc
# List corresponding compiled object files here (.o files)
SIM_OBJ = main.o cache.o NewCache.o
#################################
# default rule
all: sim_cache
@echo "my work is done here..."
# rule for making sim_cache
sim_cache: $(SIM_OBJ)
$(CC) -o sim_cache $(CFLAGS) $(SIM_OBJ) -lm
@echo "-----------DONE WITH SIM_CACHE-----------"
# generic rule for converting any .cc file to any .o file
.cc.o:
$(CC) $(CFLAGS) -c $*.cc
# type "make clean" to remove all .o files plus the sim_cache binary
clean:
rm -f *.o sim_cache
# type "make clobber" to remove all .o files (leaves sim_cache binary)
clobber:
rm -f *.o

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#include "NewCache.h"
Config::Config(char *argv[])
{
blockSize = atoi(argv[1]);
L1_size = atoi(argv[2]);
L2_size = atoi(argv[3]);
L1_assoc = atoi(argv[4]);
L2_assoc = atoi(argv[5]);
victimCacheSize = atoi(argv[6]);
trace_file = std::string(argv[7]);
}
void Config::printConfig()
{
cout << setiosflags(ios::left);
cout << "===== Simulator configuration =====" << endl;
cout << setw(30) << "BLOCKSIZE:" << this->blockSize << endl;
cout << setw(30) << "L1_SIZE:" << this->L1_size << endl;
cout << setw(30) << "L1_ASSOC:" << this->L1_assoc << endl;
cout << setw(30) << "Victim_Cache_SIZE:" << this->victimCacheSize << endl;
cout << setw(30) << "L2_SIZE:" << this->L2_size << endl;
cout << setw(30) << "L2_ASSOC:" << this->L2_assoc << endl;
cout << setw(30) << "trace_file:" << this->trace_file << endl;
cout << "===================================" << endl;
}
NewCache::NewCache(Config *config)
{
this->config = config;
if (config->L2_size > 0)
{
Cache *l2 = new Cache(config->blockSize, config->L2_size, config->L2_assoc, 0, "L2");
cache = new Cache(config->blockSize, config->L1_size, config->L1_assoc, config->victimCacheSize, l2, "L1");
m = new Monitor(cache->GetStatis(), l2->GetStatis(), config->L2_size, config->victimCacheSize);
}
else
{
cache = new Cache(config->blockSize, config->L1_size, config->L1_assoc, config->victimCacheSize, nullptr, "L1");
m = new Monitor(cache->GetStatis(), nullptr, config->L2_size, config->victimCacheSize);
}
}

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#pragma once
#include "cache.h"
#include <cstdint>
#include <fstream>
#include <iostream>
using namespace std;
class Config
{
public:
int blockSize;
int L1_size;
int L2_size;
int L1_assoc;
int L2_assoc;
int victimCacheSize;
string trace_file;
Config(char *argv[]);
void printConfig();
};
class NewCache
{
public:
Config *config;
Cache *cache;
Monitor *m;
NewCache(Config *config);
~NewCache();
};

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#include "cache.h"
#include <algorithm>
#include <cstdint>
#include <exception>
#include <fstream>
#include <iostream>
using namespace std;
int CacheParam::getBlockSize() { return blockSize; }
int CacheParam::Size() { return s; }
int CacheParam::Assoc() { return assoc; }
int CacheParam::ReplicementPolicy() { return replicementPolicy; }
int CacheParam::WritePolicy() { return writePolicy; }
CacheParam::CacheParam(){}
CacheParam::CacheParam(int blockSize, int size, int ass, int vis, int rep, int wrp)
{
this->blockSize = blockSize;
this->s = size;
this->assoc = ass;
this->victimSize = vis;
this->replicementPolicy = rep;
this->writePolicy = wrp;
setupTIO();
}
double CacheParam::GetHT()
{
return 0.25 + 2.5 * (s / (512.0 * 1024)) + 0.025 * (blockSize / 16.0) + 0.025 * assoc;
}
double CacheParam::GetHT2()
{
return 2.5 + 2.5 * (s / (512.0 * 1024)) + 0.025 * (blockSize / 16.0) + 0.025 * assoc;
}
double CacheParam::GetMP()
{
return 20 + 0.5 * (blockSize / 16.0);
}
int CacheParam::log2_floor(uint32_t x)
{
return x == 0 ? -1 : 31 - __builtin_clz(x);
}
uint32_t CacheParam::GetMaxIndex()
{
return (1 << i);
}
uint32_t CacheParam::GetVictimAs()
{
return victimAsso;
}
uint32_t CacheParam::GetAs()
{
return assoc;
}
void CacheParam::setupTIO()
{
// setup t, i, b
o = log2_floor(blockSize);
i = log2_floor(s / (blockSize * assoc));
t = 32 - o - i;
om = (1 << o) - 1;
im = ((1 << i) - 1) << o;
if (!victimSize)
return;
vo = log2_floor(blockSize);
vi = 0;
vt = 32 - vo - vi;
victimAsso = victimSize / blockSize;
vom = (1 << vo) - 1;
// vim = ((1<<vi)-1) << vo;
}
CacheTIO CacheParam::VictimAddrParser(uint32_t addr)
{
uint32_t offset = addr & vom;
// uint32_t index = (addr & vim) >> vo;
uint32_t tag = addr >> vo;
return {tag, 0, offset, addr};
}
CacheTIO CacheParam::AddrParser(uint32_t addr)
{
uint32_t offset = addr & om;
uint32_t index = (addr & im) >> o;
uint32_t tag = addr >> (o + i);
return {tag, index, offset, addr};
}
uint32_t CacheParam::UnParser(uint32_t tag, CacheTIO tio)
{
return (tag << (o + i)) | (tio.index << o) | (tio.offset);
}
uint32_t CacheParam::UnParserVic(uint32_t tag, CacheTIO tio)
{
return (tag << (vo)) | (tio.offset);
}
Cache::Cache(int blockSize, int s, int assoc, int victimSize, string l, int replicementPolicy, int writePolicy)
{
p = CacheParam(blockSize, s, assoc, victimSize, replicementPolicy, writePolicy);
st.SetCP(&p);
c.resize(p.GetMaxIndex());
this->level = l;
for (auto &b : c)
b.resize(p.GetAs());
if (victimSize)
vc.resize(p.GetVictimAs());
}
Cache::Cache(int blockSize, int s, int assoc, int victimSize, Cache *n, string l, int replicementPolicy, int writePolicy)
{
p = CacheParam(blockSize, s, assoc, victimSize, replicementPolicy, writePolicy);
st.SetCP(&p);
c.resize(p.GetMaxIndex());
for (auto &b : c)
b.resize(p.GetAs());
if (victimSize)
vc.resize(p.GetVictimAs());
NextCache = n;
level = l;
}
void Cache::Visit(uint32_t rawAddr, bool isWrite)
{
isWrite ? st.Write() : st.Read();
auto addr = p.AddrParser(rawAddr);
auto s = &c[addr.index];
// Find in Cache
auto cl = find_if(
s->begin(),
s->end(),
[=](const Block &b)
{
return b.v && b.tag == addr.tag;
});
if (cl != s->end())
{
// Cache Hit!
for (auto &b : (*s))
b.lru += (b.lru < cl->lru);
cl->lru = 0;
cl->d |= isWrite;
return;
}
// Main Cache Miss
cl = find_if(
s->begin(),
s->end(),
[](const Block &b)
{
return !b.v;
});
if (cl == s->end())
{
// Replace
cl = max_element(
s->begin(),
s->end());
}
if (!vc.size())
{
isWrite ? st.WriteMiss() : st.ReadMiss();
// No Victim Cache
if (cl->v && cl->d)
{
// Write to the L2 or Disk
st.WriteBack();
if (NextCache != nullptr)
{
NextCache->Visit(p.UnParser(cl->tag, addr), true);
}
}
if (NextCache != nullptr)
{
// 2. Find it from Next Level
NextCache->Visit(rawAddr, false);
}
for (auto &b : (*s))
b.lru++;
*cl = {addr.tag, 0, isWrite, true};
}
else
{
// Has Victim Cache: Replace with Victim
// Miss Write or Read Miss, Go to Next Level
// 1. Find it from Victim Cache
auto vaddr = p.VictimAddrParser(rawAddr);
auto vcp = &vc;
auto vic = find_if(
vcp->begin(),
vcp->end(),
[=](const Block &b)
{
return b.v && b.tag == vaddr.tag;
});
if (vic != vcp->end())
{
// V. Cache Hit from Victim!
auto tmp = *vic;
if (cl->v)
{
for (auto &b : *vcp)
b.lru += (b.lru < tmp.lru);
*vic = {p.VictimAddrParser(p.UnParser(cl->tag, addr)).tag, 0, cl->d, true};
}
for (auto &b : (*s))
b.lru++;
*cl = {addr.tag, 0, isWrite || tmp.d, true};
st.Exchange();
return;
}
// X. Victim Cache Miss!
isWrite ? st.WriteMiss() : st.ReadMiss();
if (!cl->v)
{
if (NextCache != nullptr)
{
// 2. Find it from Next Level
NextCache->Visit(rawAddr, false);
}
// Empty Level 1
for (auto &b : (*s))
b.lru++;
*cl = {addr.tag, 0, isWrite, true};
return;
}
vic = find_if(
vcp->begin(),
vcp->end(),
[=](const Block &b)
{
return !b.v;
});
if (vic == vcp->end())
{
// Vic Full, find one to deprecate
vic = max_element(
vcp->begin(),
vcp->end());
if (vic->v && vic->d)
{
st.WriteBack();
if (NextCache != nullptr)
{
NextCache->Visit(p.UnParserVic(vic->tag, vaddr), true);
}
}
}
// New Victim Cache
for (auto &b : *vcp)
b.lru++;
*vic = {p.VictimAddrParser(p.UnParser(cl->tag, addr)).tag, 0, cl->d, true};
for (auto &b : (*s))
b.lru++;
*cl = {addr.tag, 0, isWrite, true};
if (NextCache != nullptr)
{
// 2. Find it from Next Level
NextCache->Visit(rawAddr, false);
}
}
return;
}

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#pragma once
#include "public.h"
#include <algorithm>
#include <bitset>
#include <cstdint>
#include <exception>
#include <iomanip>
#include <ostream>
#include <vector>
using namespace std;
struct CacheTIO
{
uint32_t tag, index, offset, rAddr;
};
class CacheParam
{
public:
int blockSize; // Block Size
int s; // Size
int assoc; // Assoc
int replicementPolicy; // Replicement Policy
int writePolicy; // Write Policy: 1 -> WTNA, 0 ->
int victimSize; // Victim Size
int victimAsso; // Victim Asso
int t; // tag bit
int i; // index
int o; // offset
uint32_t om; // offset mask
uint32_t im; // index mask
int vt; // victim tag bit
int vi; // victim index
int vo; // victim offset
uint32_t vom; // victim offset mask
uint32_t vim; // victim index mask
CacheParam();
CacheParam(int blockSize, int size, int ass, int vis, int rep, int wrp);
double GetHT();
double GetHT2();
double GetMP();
int log2_floor(uint32_t x);
uint32_t GetMaxIndex();
uint32_t GetVictimAs();
uint32_t GetAs();
void setupTIO();
CacheTIO VictimAddrParser(uint32_t addr);
CacheTIO AddrParser(uint32_t addr);
uint32_t UnParser(uint32_t tag, CacheTIO tio);
uint32_t UnParserVic(uint32_t tag, CacheTIO tio);
int getBlockSize();
int Size();
int Assoc();
int ReplicementPolicy();
int WritePolicy();
};
struct Block
{
uint32_t tag = 0; // tag
uint32_t lru = 0; // Last Used
bool d = false; // dirty
bool v = false; // valid
bool operator<(const Block &t) const { return lru < t.lru; }
void printBlock()
{
cout << "{tag:" << this->tag << ", LRU:" << this->lru << ", Dirty:" << this->d << ", Valid:" << this->v << "}";
}
};
class Statistic
{
public:
int r = 0; // Read Count
int rm = 0; // Read Miss
int w = 0; // Write Count
int wm = 0; // Write Miss
int wb = 0; // Write Back
int ex = 0; // Exchange (between L1 and Victim)
CacheParam *p;
public:
void SetCP(CacheParam *cp) { p = cp; }
void Read() { r++; }
void ReadMiss() { rm++; }
void Write() { w++; }
void WriteMiss() { wm++; }
void WriteBack() { wb++; }
void Exchange() { ex++; }
int GetCommunication() { return rm + wm + wb; }
double GetMR()
{
return (double)(rm + wm) / (double)(r + w);
}
double GetMR2()
{
return (double)(rm) / (double)(r);
}
double GetAAT()
{
double HT = p->GetHT();
double MP = p->GetMP();
double MR = GetMR();
return HT + (MP * MR);
}
friend ostream &operator<<(ostream &cout, const Statistic &st)
{
cout << "\n ====== Simulation results (raw) ======\n";
cout << " a. number of L1 reads:" << setw(16) << st.r << endl;
cout << " b. number of L1 read misses:" << setw(10) << st.rm << endl;
cout << " c. number of L1 writes:" << setw(15) << st.w << endl;
cout << " d. number of L1 write misses:" << setw(9) << st.wm << endl;
double mr = (st.rm + st.wm) / (double)(st.r + st.w);
cout << " e. L1 miss rate:" << setw(22) << fixed << setprecision(4) << mr << endl;
cout << " f. number of writebacks from L1:" << setw(6) << st.wb << endl;
cout << " g. total memory traffic:" << setw(14) << ((st.p->WritePolicy()) ? (st.rm + st.w) : (st.rm + st.wm + st.wb));
cout << "\n\n ==== Simulation results (performance) ====\n";
double ht = st.p->GetHT();
double mp = st.p->GetMP();
cout << " 1. average access time:" << setw(15) << ht + mr * mp << " ns";
return cout;
}
};
class Monitor
{
public:
Statistic *l1, *l2;
bool Has2, HasV;
Monitor() {}
Monitor(Statistic *s1, Statistic *s2, bool h2, bool hv)
{
l1 = s1, l2 = s2;
Has2 = h2, HasV = hv;
}
friend ostream &operator<<(ostream &cout, Monitor &m)
{
cout << "====== Simulation results (raw) ======" << endl;
cout << setw(38) << "a. number of L1 reads: " << m.l1->r << endl;
cout << setw(38) << "b. number of L1 read misses: " << m.l1->rm << endl;
cout << "c. number of L1 writes: " << m.l1->w << endl;
cout << setw(38) << "d. number of L1 write misses: " << m.l1->wm << endl;
cout << setw(38) << "e. L1 miss rate: " << fixed << setprecision(4) << m.l1->GetMR() << endl;
cout << setw(38) << "f. number of swaps: " << m.l1->ex << endl;
cout << setw(38) << "g. number of victim cache writeback: " << (m.HasV ? m.l1->wb : 0) << endl;
if (m.Has2)
{
cout << setw(38) << "h. number of L2 reads: " << m.l2->r << endl;
cout << setw(38) << "i. number of L2 read misses: " << m.l2->rm << endl;
cout << setw(38) << "j. number of L2 writes: " << m.l2->w << endl;
cout << setw(38) << "k. number of L2 write misses: " << m.l2->wm << endl;
cout << setw(38) << "l. L2 miss rate: " << fixed << setprecision((m.Has2) ? 4 : 0) << m.l2->GetMR2() << endl;
cout << setw(38) << "m. number of L2 writebacks: " << m.l2->wb << endl;
cout << setw(38) << "n. total memory traffic: " << (m.l2->rm + m.l2->wm + m.l2->wb) << endl;
cout << "==== Simulation results (performance) ====" << endl;
double HT1 = m.l1->p->GetHT(), MR1 = m.l1->GetMR();
double HT2 = m.l2->p->GetHT2(), MR2 = m.l2->GetMR2();
double MP = m.l2->p->GetMP();
cout << setw(32) << "1. average access time:" << fixed << setprecision(4) << HT1 + (MR1 * (HT2 + MR2 * MP)) << " ns" << endl;
}
else
{
cout << setw(38) << "h. number of L2 reads: " << 0 << endl;
cout << setw(38) << "i. number of L2 read misses: " << 0 << endl;
cout << setw(38) << "j. number of L2 writes: " << 0 << endl;
cout << setw(38) << "k. number of L2 write misses: " << 0 << endl;
cout << setw(38) << "l. L2 miss rate: " << 0 << endl;
cout << setw(38) << "m. number of L2 writebacks: " << 0 << endl;
cout << setw(38) << "n. total memory traffic: " << (m.l1->rm + m.l1->wm + m.l1->wb) << endl;
cout << "==== Simulation results (performance) ====" << endl;
double ht = m.l1->p->GetHT();
double mp = m.l1->p->GetMP();
double mr = (m.l1->rm + m.l1->wm) / (double)(m.l1->r + m.l1->w);
cout << setw(32) << "1. average access time:" << fixed << setprecision(4) << ht + mr * mp << " ns" << endl;
}
return cout;
}
};
class Cache
{
public:
CacheParam p;
Statistic st;
vector<vector<Block>> c; // Cache
vector<Block> vc; // Victim Cache
string level;
Cache *NextCache = nullptr;
Cache(int blockSize, int s, int assoc, int victimSize, string l = "L1", int replicementPolicy = LRU, int writePolicy = LFU);
Cache(int blockSize, int s, int assoc, int victimSize, Cache *n = nullptr, string l = "L1", int replicementPolicy = LRU, int writePolicy = LFU);
~Cache()
{
delete NextCache;
}
Statistic *GetStatis() { return &st; }
void Visit(uint32_t rawAddr, bool isWrite);
void printCache()
{
if (!this->p.Size())
return;
cout << "===== " << this->level << " contents =====" << endl;
for (unsigned i = 0; i != this->c.size(); i++)
{
cout << "set " << i << ": ";
auto temp = this->c[i];
stable_sort(temp.begin(), temp.end());
for (auto b : temp)
cout << hex << b.tag << (b.d ? " D " : " ");
cout << endl
<< dec;
}
if (this->vc.size())
{
cout << "===== Victim Cache contents =====" << endl;
cout << "set 0: ";
auto temp = this->vc;
stable_sort(temp.begin(), temp.end());
for (auto b : temp)
cout << hex << b.tag << (b.d ? " D " : " ");
cout << endl
<< dec;
}
}
};

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#include "public.h"
#include "NewCache.h"
#include "cache.h"
using namespace std;
int main(int argc, char *argv[])
{
Config *config;
NewCache *newCache;
try
{
config = new Config(argv);
newCache = new NewCache(config);
}
catch (...)
{
cout << "Init err." << endl;
}
try
{
ifstream trace("../traces/" + config->trace_file);
string line;
char op;
unsigned addr;
while (getline(trace, line) && (istringstream(line) >> op >> hex >> addr))
{
newCache->cache->Visit(addr, op == 'w');
}
trace.close();
}
catch (const std::exception &e)
{
cout << "run err." << endl;
std::cerr << e.what() << '\n';
}
// 输出
config->printConfig();
newCache->cache->printCache();
if (newCache->m->Has2)
(newCache->cache->NextCache)->printCache();
cout << (*newCache->m);
return 0;
}

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#pragma once
#define LRU 0
#define LFU 1
#define WBWA 0
#define WTNA 1
#define WRITE 1
#define READ 0
#include <algorithm>
#include <cstdint>
#include <exception>
#include <fstream>
#include <iostream>
#include <cstdlib>
#include <sstream>
#include <stdexcept>
#include <stdlib.h>
#include <stdio.h>
#include <sys/stat.h>

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make clean
make
./sim_cache 32 2048 4096 4 8 0 gcc_trace.txt > ../output/test1.txt
./sim_cache 16 1024 8192 8 4 0 go_trace.txt > ../output/test2.txt
./sim_cache 32 1024 0 8 0 256 perl_trace.txt > ../output/test3.txt
./sim_cache 128 1024 4096 2 4 1024 gcc_trace.txt > ../output/test4.txt
./sim_cache 64 8192 16384 2 4 1024 perl_trace.txt > ../output/test5.txt
echo "Comparing 1 :"
diff -iw ../output/test1.txt ../validation/Validation6_PartB.txt
echo "Comparing 2 :"
diff -iw ../output/test2.txt ../validation/Validation7_PartB.txt
echo "Comparing 3 :"
diff -iw ../output/test3.txt ../validation/Validation8_PartB.txt
echo "Comparing 4 :"
diff -iw ../output/test4.txt ../validation/Validation9_PartB.txt
echo "Comparing 5 :"
diff -iw ../output/test5.txt ../validation/Validation10_PartB.txt