61 lines
3.2 KiB
Plaintext
61 lines
3.2 KiB
Plaintext
===== Simulator configuration =====
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BLOCKSIZE: 32
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L1_SIZE: 2048
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L1_ASSOC: 4
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Victim_Cache_SIZE: 0
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L2_SIZE: 4096
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L2_ASSOC: 8
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trace_file: gcc_trace.txt
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===================================
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===== L1 contents =====
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set 0: 20028d D 20018a 20028e D 200198 D
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set 1: 2001c1 D 20028d D 200153 D 20013b
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set 2: 200223 D 20028d D 200241 2001c1
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set 3: 20018a 2001ac D 20028e D 20028d D
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set 4: 20018f D 2000f9 20017a D 20018a
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set 5: 200009 20017a 2000fa 20018a
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set 6: 200009 2000f9 20028d D 20018a
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set 7: 200009 2001ac 2000fa 200149
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set 8: 200009 3d819c D 20017b D 2000f9
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set 9: 200009 2000fa 2000f9 2001b2 D
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set 10: 200009 200214 2000fa 20023f
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set 11: 200009 2001ab 20013a 20023f
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set 12: 20018f D 2001f2 2001aa 20018a D
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set 13: 20028d D 20018d D 20013a 20028c D
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set 14: 20013a 20018d D 20028d D 2001ad D
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set 15: 2001f8 D 20028c D 20013a 20018d D
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===== L2 contents =====
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set 0: 20018a 20028e 200198 2001ab 2001d1 D 20017a D 20028d 2001f4 D
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set 1: 2001c1 200153 D 20028e D 20013b 200198 D 2000fb 2001d1 D 20028d
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set 2: 200241 20028d D 200223 200149 200198 D 20018a 2001c1 D 20013b
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set 3: 2001ac 2001c1 D 20028e 2001b0 D 20028d 20028c D 20018a 2001bd D
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set 4: 2000f9 20028e D 20018a 20028d D 20017a D 20023f 200149 2002b1 D
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set 5: 20017a 20028e D 200009 20028d D 2000fa 2001b2 D 20018a 20023f
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set 6: 200009 2000f9 2001b2 D 20023f 2001ac D 2001ad D 20028d 20028c D
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set 7: 200009 20028d D 2000fa 2001b2 D 2001ac 20023f 200149 2001f6 D
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set 8: 200009 20017b D 2000fa 2001b2 D 2000f9 20028d D 20023f 200149
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set 9: 200009 2000fa 20028d D 2001b2 20023f 3d819c D 20028c D 2001aa
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set 10: 200009 200214 D 20028d D 20023f 2001ab D 2001aa 2001fc D 2000fa
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set 11: 200009 2001ab 20028d D 20023f 2001aa 200214 D 20028c D 20013a
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set 12: 20018f 2001aa 20018a 2001f2 20023f 20028d D 20018d D 2001ab
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set 13: 20028d 2001b3 D 20018d 2001ab D 20013a 2001b2 D 20028c 2001fe D
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set 14: 20028d 20028c D 20018d 2001a7 D 20013a 2001b2 D 2001ad D 2001fd D
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set 15: 20013a 20028d D 20018d 200197 D 2001f8 2001a9 D 200222 D 2001d1 D
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====== Simulation results (raw) ======
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a. number of L1 reads: 63640
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b. number of L1 read misses: 5170
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c. number of L1 writes: 36360
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d. number of L1 write misses: 4452
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e. L1 miss rate: 0.0962
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f. number of swaps: 0
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g. number of victim cache writeback: 0
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h. number of L2 reads: 9622
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i. number of L2 read misses: 5313
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j. number of L2 writes: 4942
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k. number of L2 write misses: 151
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l. L2 miss rate: 0.5522
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m. number of L2 writebacks: 2978
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n. total memory traffic: 8442
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==== Simulation results (performance) ====
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1. average access time: 1.7920 ns
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