finish 1-1
This commit is contained in:
parent
a6f51e4558
commit
0d74de5c34
|
|
@ -0,0 +1,7 @@
|
|||
{
|
||||
"files.associations": {
|
||||
"iomanip": "cpp",
|
||||
"iosfwd": "cpp",
|
||||
"vector": "cpp"
|
||||
}
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,24 @@
|
|||
===== Simulator configuration =====
|
||||
L1_BLOCKSIZE: 128
|
||||
L1_SIZE: 2048
|
||||
L1_ASSOC: 8
|
||||
L1_REPLACEMENT_POLICY: 0
|
||||
L1_WRITE_POLICY: 1
|
||||
trace_file: go_trace.txt
|
||||
===================================
|
||||
|
||||
===== L1 contents =====
|
||||
set 0: 4004e0 400321 40031f 40040c 400320 40040b 4004e1 40040d
|
||||
set 1: 40040c 4004e1 4008b3 400652 400320 40031f 40040d 4004e0
|
||||
|
||||
====== Simulation results (raw) ======
|
||||
a. number of L1 reads: 60613
|
||||
b. number of L1 read misses: 984
|
||||
c. number of L1 writes: 39387
|
||||
d. number of L1 write misses: 26075
|
||||
e. L1 miss rate: 0.2706
|
||||
f. number of writebacks from L1: 0
|
||||
g. total memory traffic: 40371
|
||||
|
||||
==== Simulation results (performance) ====
|
||||
1. average access time: 7.1539 ns
|
||||
|
|
@ -0,0 +1,54 @@
|
|||
===== Simulator configuration =====
|
||||
L1_BLOCKSIZE: 32
|
||||
L1_SIZE: 4096
|
||||
L1_ASSOC: 4
|
||||
L1_REPLACEMENT_POLICY: 0
|
||||
L1_WRITE_POLICY: 1
|
||||
trace_file: perl_trace.txt
|
||||
===================================
|
||||
|
||||
===== L1 contents =====
|
||||
set 0: 10007a 10006d 10007b 100075
|
||||
set 1: 1000b4 10007b 100073 100035
|
||||
set 2: 100035 10007b 1000b3 1000b4
|
||||
set 3: 1000b0 1000a1 100035 10007b
|
||||
set 4: 100035 10006f 1000b4 10007b
|
||||
set 5: 10007b 100058 10007a 10006f
|
||||
set 6: 100079 1000a1 10006f 10007a
|
||||
set 7: 100035 1000a1 10007a 1000b3
|
||||
set 8: 10007b 10007a 1000b4 1000a1
|
||||
set 9: 10007a 10006f 100079 10007b
|
||||
set 10: 1000b2 1000ad 1000ae 10007a
|
||||
set 11: 10002e 1000b2 1000a9 10007a
|
||||
set 12: 1ec0cf 1000a9 100035 10007a
|
||||
set 13: 10007a 1000ad 1ec0cf 10006f
|
||||
set 14: 1000b2 1000b3 1000ad 10007a
|
||||
set 15: 10007a 1000ad 1000b2 1000b3
|
||||
set 16: 10006f 1000b3 1000b0 1000ad
|
||||
set 17: 1000b2 1000b1 1000ad 1000af
|
||||
set 18: 1000b1 1000b3 1000b2 1000ad
|
||||
set 19: 1000ab 1000b3 1000ad 1ec0cf
|
||||
set 20: 1000b3 1000ad 1000aa 10007a
|
||||
set 21: 1000ad 1000b2 100008 10007a
|
||||
set 22: 1ec0cf 10007a 100008 1000b3
|
||||
set 23: 1000b2 1000b3 100064 1ec0cf
|
||||
set 24: 1000b0 1000a0 1000af 100077
|
||||
set 25: 1000ab 1000b1 1000b2 1000b0
|
||||
set 26: 10004e 1000b3 100031 10004c
|
||||
set 27: 1000b3 1ec0cf 10004e 100031
|
||||
set 28: 10007a 1000b0 1000af 1000a0
|
||||
set 29: 1ec0ce 1000b0 10007a 1000b3
|
||||
set 30: 1000b3 1ec0ce 1000b1 1000b2
|
||||
set 31: 100074 1000b3 100077 1000b1
|
||||
|
||||
====== Simulation results (raw) ======
|
||||
a. number of L1 reads: 70107
|
||||
b. number of L1 read misses: 4739
|
||||
c. number of L1 writes: 29893
|
||||
d. number of L1 write misses: 6850
|
||||
e. L1 miss rate: 0.1159
|
||||
f. number of writebacks from L1: 0
|
||||
g. total memory traffic: 34632
|
||||
|
||||
==== Simulation results (performance) ====
|
||||
1. average access time: 2.8532 ns
|
||||
|
|
@ -0,0 +1,86 @@
|
|||
===== Simulator configuration =====
|
||||
L1_BLOCKSIZE: 64
|
||||
L1_SIZE: 8192
|
||||
L1_ASSOC: 2
|
||||
L1_REPLACEMENT_POLICY: 1
|
||||
L1_WRITE_POLICY: 0
|
||||
trace_file: gcc_trace.txt
|
||||
===================================
|
||||
|
||||
===== L1 contents =====
|
||||
set 0: 40033 D 7b035 D
|
||||
set 1: 40056 D 40033 D
|
||||
set 2: 7b035 D 4001f
|
||||
set 3: 40056 D 40055 D
|
||||
set 4: 40055 D 40056 D
|
||||
set 5: 40056 D 7b035 D
|
||||
set 6: 42355 4001f
|
||||
set 7: 4003f D 40056 D
|
||||
set 8: 40038 D 40056 D
|
||||
set 9: 40048 40038 D
|
||||
set 10: 40029 40001
|
||||
set 11: 4001f 40001
|
||||
set 12: 40001 4001f
|
||||
set 13: 40001 40051 D
|
||||
set 14: 40031 D 40051 D
|
||||
set 15: 40035 D 40051 D
|
||||
set 16: 40051 D 40031
|
||||
set 17: 40051 D 40031
|
||||
set 18: 4002f 40031
|
||||
set 19: df8 4001f
|
||||
set 20: 4001f 40036 D
|
||||
set 21: 4001f 40027
|
||||
set 22: 40027 4003e
|
||||
set 23: 40027 40051 D
|
||||
set 24: 4002a D 4001f
|
||||
set 25: df8 40044 D
|
||||
set 26: 40051 D 4003e D
|
||||
set 27: 40037 D 40051 D
|
||||
set 28: 40051 D 4002f D
|
||||
set 29: 40035 D 40051 D
|
||||
set 30: 40051 D 40035
|
||||
set 31: 40055 D 40051 D
|
||||
set 32: 40136 D 4003e D
|
||||
set 33: 40035 D 40051 D
|
||||
set 34: 40051 D 40055 D
|
||||
set 35: 40035 D 40051 D
|
||||
set 36: 40138 D 7b033 D
|
||||
set 37: 7b033 D 40042 D
|
||||
set 38: 40051 D 40055 D
|
||||
set 39: 40051 D 40055 D
|
||||
set 40: 7b033 D 40051 D
|
||||
set 41: 40051 D 40055 D
|
||||
set 42: 40051 D 40055 D
|
||||
set 43: 40051 D 40055 D
|
||||
set 44: 40051 D 40055 D
|
||||
set 45: 40055 D 40051 D
|
||||
set 46: 40051 D 40031 D
|
||||
set 47: 40051 D 40031 D
|
||||
set 48: 40051 D 40055 D
|
||||
set 49: 40055 D 40051 D
|
||||
set 50: 7b034 D 40051 D
|
||||
set 51: 7b034 D 4003e D
|
||||
set 52: 40054 D 40055 D
|
||||
set 53: 7b034 D 40035
|
||||
set 54: 4003f D 40055 D
|
||||
set 55: 40036 D 40055 D
|
||||
set 56: 40055 D 40039
|
||||
set 57: 40022 D 4003e D
|
||||
set 58: 40031 D 40047
|
||||
set 59: 40047 40055 D
|
||||
set 60: 40047 7b034 D
|
||||
set 61: 7b034 D 40047
|
||||
set 62: 4001e 40031 D
|
||||
set 63: 4001c 40032 D
|
||||
|
||||
====== Simulation results (raw) ======
|
||||
a. number of L1 reads: 63640
|
||||
b. number of L1 read misses: 3492
|
||||
c. number of L1 writes: 36360
|
||||
d. number of L1 write misses: 2096
|
||||
e. L1 miss rate: 0.0559
|
||||
f. number of writebacks from L1: 2415
|
||||
g. total memory traffic: 8003
|
||||
|
||||
==== Simulation results (performance) ====
|
||||
1. average access time: 1.6684 ns
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
===== Simulator configuration =====
|
||||
L1_BLOCKSIZE: 32
|
||||
L1_SIZE: 1024
|
||||
L1_ASSOC: 4
|
||||
L1_REPLACEMENT_POLICY: 1
|
||||
L1_WRITE_POLICY: 1
|
||||
trace_file: go_trace.txt
|
||||
===================================
|
||||
|
||||
===== L1 contents =====
|
||||
set 0: 4004e0 400321 40040d 4004e1
|
||||
set 1: 4004e0 4004e1 40040d 4004df
|
||||
set 2: 4004df 4004e1 40040d 4004e0
|
||||
set 3: 4004e1 4004e0 4004df 40040d
|
||||
set 4: 4004e1 4008b3 40040d 400652
|
||||
set 5: 4004e0 4004df 400320 40040c
|
||||
set 6: 4004df 40040c 4004e0 4004de
|
||||
set 7: 40040c 4004df 4004e0 400320
|
||||
|
||||
====== Simulation results (raw) ======
|
||||
a. number of L1 reads: 60613
|
||||
b. number of L1 read misses: 4893
|
||||
c. number of L1 writes: 39387
|
||||
d. number of L1 write misses: 33648
|
||||
e. L1 miss rate: 0.3854
|
||||
f. number of writebacks from L1: 0
|
||||
g. total memory traffic: 44280
|
||||
|
||||
==== Simulation results (performance) ====
|
||||
1. average access time: 8.4985 ns
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
CC = g++
|
||||
OPT = -O3 -m32
|
||||
#OPT = -g -m32
|
||||
#OPT = -O3 -m32
|
||||
OPT = -g
|
||||
WARN = -Wall
|
||||
CFLAGS = $(OPT) $(WARN) $(INC) $(LIB)
|
||||
|
||||
|
|
|
|||
|
|
@ -40,7 +40,7 @@ Cache::Cache(char *argv[])
|
|||
this->indexMask = ((1 << this->index) - 1) << this->offset;
|
||||
|
||||
this->L1.resize(this->getMaxIndex());
|
||||
for (auto &s : L1 )
|
||||
for (auto &s : L1)
|
||||
s.block.resize(this->getAssoc());
|
||||
}
|
||||
|
||||
|
|
@ -48,13 +48,22 @@ Cache::~Cache()
|
|||
{
|
||||
}
|
||||
|
||||
uint32_t Cache::getMaxIndex(){
|
||||
return (1<<this->index);
|
||||
void Cache::StWrite() { this->writeCount++; }
|
||||
void Cache::StWriteMiss() { this->writeMiss++; }
|
||||
void Cache::StRead() { this->readCount++; }
|
||||
void Cache::StReadMiss() { this->readMiss++; }
|
||||
void Cache::StWriteBack() { this->writeBack++; }
|
||||
|
||||
uint32_t Cache::getMaxIndex()
|
||||
{
|
||||
return (1 << this->index);
|
||||
}
|
||||
uint32_t Cache::getAssoc() {
|
||||
uint32_t Cache::getAssoc()
|
||||
{
|
||||
return this->assoc;
|
||||
}
|
||||
int Cache::log2_floor(uint32_t x) {
|
||||
}
|
||||
int Cache::log2_floor(uint32_t x)
|
||||
{
|
||||
return x == 0 ? -1 : 31 - __builtin_clz(x);
|
||||
}
|
||||
CacheTIO Cache::Address2TIO(uint32_t addr)
|
||||
|
|
@ -65,8 +74,81 @@ CacheTIO Cache::Address2TIO(uint32_t addr)
|
|||
return {tag, index, offset};
|
||||
}
|
||||
|
||||
void Cache::writeCache(uint32_t address){
|
||||
void Cache::useCache(uint32_t address, int method)
|
||||
{
|
||||
|
||||
(method == WRITE)?this->StWrite():this->StRead();
|
||||
|
||||
auto addr = this->Address2TIO(address);
|
||||
auto set = &L1[addr.index];
|
||||
auto tag = addr.tag;
|
||||
|
||||
auto hit = find_if(
|
||||
set->block.begin(),
|
||||
set->block.end(),
|
||||
[tag](const Block &b)
|
||||
{
|
||||
return b.valid && b.tag == tag;
|
||||
});
|
||||
|
||||
if (hit != set->block.end())
|
||||
{
|
||||
// Cache Hit!
|
||||
hit->countBlock++;
|
||||
hit->lastUsed = this->lru++;
|
||||
if (method == WRITE && this->writePolicy == WBWA)
|
||||
{
|
||||
hit->dirty = true;
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
if (method == WRITE)
|
||||
{
|
||||
this->StWriteMiss();
|
||||
}
|
||||
else
|
||||
{
|
||||
this->StReadMiss();
|
||||
}
|
||||
|
||||
if (method == WRITE && this->writePolicy == WTNA)
|
||||
return;
|
||||
|
||||
auto toReplace = find_if(
|
||||
set->block.begin(),
|
||||
set->block.end(),
|
||||
[](const Block& b){
|
||||
return !b.valid;
|
||||
}
|
||||
);
|
||||
|
||||
if (toReplace == set->block.end()){
|
||||
// Replace
|
||||
toReplace = min_element(
|
||||
set->block.begin(),
|
||||
set->block.end(),
|
||||
this->replicementPolicy == LRU
|
||||
?
|
||||
[](const Block &a, const Block &b){ return a.lastUsed < b.lastUsed; }
|
||||
:
|
||||
[](const Block&a, const Block&b){ return a.countBlock < b.countBlock; }
|
||||
);
|
||||
}
|
||||
|
||||
if (toReplace->dirty) {
|
||||
// Write to the L2 or Disk
|
||||
this->StWriteBack();
|
||||
}
|
||||
|
||||
set->countSet = toReplace->countBlock;
|
||||
|
||||
*toReplace = {addr.tag, set->countSet + 1, lru ++, (bool)method, true};
|
||||
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
void Cache::printResult(){
|
||||
return ;
|
||||
}
|
||||
void Cache::readCache(uint32_t address);
|
||||
void Cache::useCache(uint32_t address, int method);
|
||||
|
|
@ -3,27 +3,32 @@
|
|||
#include <iostream>
|
||||
#include <ostream>
|
||||
#include <vector>
|
||||
#include <iomanip>
|
||||
|
||||
using namespace std;
|
||||
|
||||
struct CacheTIO {
|
||||
struct CacheTIO
|
||||
{
|
||||
uint32_t tag, index, offset;
|
||||
};
|
||||
|
||||
struct Block{
|
||||
struct Block
|
||||
{
|
||||
uint32_t tag = 0; // tag
|
||||
uint32_t cb = 0; // count block
|
||||
uint32_t lu = 0; // Last Used
|
||||
bool d = false; // dirty
|
||||
bool v = false; // valid
|
||||
bool operator<(const Block &t) {return cb < t.cb;}
|
||||
friend ostream& operator<<(ostream& os, Block&b) {
|
||||
os << "{tag:" << b.tag << ", Count-Block:" << b.cb << ", Last-Used:" << b.lu << ", Dirty:" << b.d << ", Valid:" << b.v << "}";
|
||||
uint32_t countBlock = 0; // count block
|
||||
uint32_t lastUsed = 0; // Last Used
|
||||
bool dirty = false; // dirty
|
||||
bool valid = false; // valid
|
||||
bool operator<(const Block &t) { return this->countBlock < t.countBlock; }
|
||||
friend ostream &operator<<(ostream &os, Block &b)
|
||||
{
|
||||
os << "{tag:" << b.tag << ", Count-Block:" << b.countBlock << ", Last-Used:" << b.lastUsed << ", Dirty:" << b.dirty << ", Valid:" << b.valid << "}";
|
||||
return os;
|
||||
}
|
||||
|
||||
};
|
||||
|
||||
struct Set {
|
||||
struct Set
|
||||
{
|
||||
uint32_t countSet = 0; // count set
|
||||
vector<Block> block; // Blocks
|
||||
};
|
||||
|
|
@ -31,7 +36,7 @@ struct Set {
|
|||
class Cache
|
||||
{
|
||||
private:
|
||||
//Param
|
||||
// Param
|
||||
int blockSize; // Block Size
|
||||
int size; // Size
|
||||
int assoc; // Assoc
|
||||
|
|
@ -45,7 +50,7 @@ private:
|
|||
uint32_t offsetMask; // offset mask
|
||||
uint32_t indexMask; // index mask
|
||||
|
||||
//Count
|
||||
// Statistic
|
||||
int readCount = 0; // Read Count
|
||||
int readMiss = 0; // Read Miss
|
||||
int writeCount = 0; // Write Count
|
||||
|
|
@ -57,17 +62,73 @@ private:
|
|||
vector<Set> L1;
|
||||
|
||||
// L2 cache
|
||||
Cache * L2;
|
||||
Cache *L2;
|
||||
|
||||
public:
|
||||
Cache(char *argv[]);
|
||||
~Cache();
|
||||
|
||||
uint32_t getMaxIndex();
|
||||
uint32_t getAssoc();
|
||||
int log2_floor(uint32_t x)
|
||||
int log2_floor(uint32_t x);
|
||||
|
||||
void StWrite();
|
||||
void StWriteMiss();
|
||||
void StRead();
|
||||
void StReadMiss();
|
||||
void StWriteBack();
|
||||
|
||||
|
||||
|
||||
void writeCache(uint32_t address);
|
||||
void readCache(uint32_t address);
|
||||
void useCache(uint32_t address, int method);
|
||||
void printResult();
|
||||
|
||||
double GetHT() {
|
||||
return 0.25 + 2.5 * (size/ (512.0 * 1024)) + 0.025 * (blockSize/ 16.0) + 0.025 * assoc;
|
||||
}
|
||||
|
||||
double GetMP() {
|
||||
return 20 + 0.5 * (blockSize / 16.0);
|
||||
}
|
||||
|
||||
|
||||
void printCache(ostream& os, Cache c,string filename){
|
||||
|
||||
os << " ===== Simulator configuration =====\n";
|
||||
os << " L1_BLOCKSIZE:" << setw(22) << c.blockSize << endl;
|
||||
os << " L1_SIZE:" << setw(27) << c.size << endl;
|
||||
os << " L1_ASSOC:" << setw(26) << c.assoc << endl;
|
||||
os << " L1_REPLACEMENT_POLICY:" << setw(13) << c.replicementPolicy << endl;
|
||||
os << " L1_WRITE_POLICY:" << setw(19) << c.writePolicy << endl;
|
||||
os << " trace_file:" << setw(24) << filename << endl;
|
||||
os << " ===================================\n\n";
|
||||
|
||||
os << "===== L1 contents =====" << endl;
|
||||
for (uint32_t i=0;i!=c.L1.size();i++){
|
||||
os << "set" << setw(4) << i << ":";
|
||||
for(auto &b:c.L1[i].block)
|
||||
os << hex << setw(8) << b.tag << ' ' << ((c.writePolicy == WBWA && b.dirty) ? 'D' : ' ');
|
||||
os << endl << dec;
|
||||
}
|
||||
|
||||
os << "\n ====== Simulation results (raw) ======\n";
|
||||
os << " a. number of L1 reads:" << setw(16) << c.readCount << endl;
|
||||
os << " b. number of L1 read misses:" << setw(10) << c.readMiss << endl;
|
||||
os << " c. number of L1 writes:" << setw(15) << c.writeCount << endl;
|
||||
os << " d. number of L1 write misses:" << setw(9) << c.writeMiss << endl;
|
||||
double mr = (c.readMiss + c.writeMiss) / (double)(c.readCount + c.writeCount);
|
||||
os << " e. L1 miss rate:" << setw(22) << fixed << setprecision(4) << mr << endl;
|
||||
os << " f. number of writebacks from L1:" << setw(6) << c.writeBack << endl;
|
||||
os << " g. total memory traffic:" << setw(14) << ((c.writePolicy) ? (c.readMiss + c.writeCount) : (c.readMiss + c.writeMiss + c.writeBack));
|
||||
os << "\n\n ==== Simulation results (performance) ====\n";
|
||||
double ht = c.GetHT();
|
||||
double mp = c.GetMP();
|
||||
os << " 1. average access time:" << setw(15) << ht + mr * mp << " ns";
|
||||
|
||||
//return os;
|
||||
}
|
||||
|
||||
CacheTIO Address2TIO(uint32_t addr);
|
||||
};
|
||||
|
|
|
|||
Binary file not shown.
|
|
@ -24,12 +24,14 @@ int main(int argc, char *argv[])
|
|||
string line;
|
||||
char op;
|
||||
unsigned addr;
|
||||
while(getline(trace, line) && (istringstream(line) >> op >> hex >> addr)) {
|
||||
while (getline(trace, line) && (istringstream(line) >> op >> hex >> addr))
|
||||
{
|
||||
cache->useCache(addr, op == 'w');
|
||||
}
|
||||
trace.close();
|
||||
cache->printCache(cout, *cache, fileName);
|
||||
}
|
||||
catch (const char* e)
|
||||
catch (const char *e)
|
||||
{
|
||||
std::cerr << "Caught exception: " << e << std::endl;
|
||||
}
|
||||
|
|
|
|||
Binary file not shown.
|
|
@ -6,6 +6,9 @@
|
|||
#define WBWA 0
|
||||
#define WTNA 1
|
||||
|
||||
#define WRITE 1
|
||||
#define READ 0
|
||||
|
||||
#include <algorithm>
|
||||
#include <cstdint>
|
||||
#include <exception>
|
||||
|
|
|
|||
Binary file not shown.
|
|
@ -0,0 +1,22 @@
|
|||
make clean
|
||||
make
|
||||
./sim_cache 16 16384 1 0 0 gcc_trace.txt > ../output/test1.txt
|
||||
./sim_cache 128 2048 8 0 1 go_trace.txt > ../output/test2.txt
|
||||
./sim_cache 32 4096 4 0 1 perl_trace.txt > ../output/test3.txt
|
||||
./sim_cache 64 8192 2 1 0 gcc_trace.txt > ../output/test4.txt
|
||||
./sim_cache 32 1024 4 1 1 go_trace.txt > ../output/test5.txt
|
||||
|
||||
echo "Comparing 1 :"
|
||||
diff -iw ../output/test1.txt ../validation/ValidationRun1.txt
|
||||
|
||||
echo "Comparing 2 :"
|
||||
diff -iw ../output/test2.txt ../validation/ValidationRun2.txt
|
||||
|
||||
echo "Comparing 3 :"
|
||||
diff -iw ../output/test3.txt ../validation/ValidationRun3.txt
|
||||
|
||||
echo "Comparing 4 :"
|
||||
diff -iw ../output/test4.txt ../validation/ValidationRun4.txt
|
||||
|
||||
echo "Comparing 5 :"
|
||||
diff -iw ../output/test5.txt ../validation/ValidationRun5.txt
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
CC = g++
|
||||
OPT = -O3 -m32
|
||||
#OPT = -g -m32
|
||||
# OPT = -O3 -m32
|
||||
OPT = -g
|
||||
WARN = -Wall
|
||||
CFLAGS = $(OPT) $(WARN) $(INC) $(LIB)
|
||||
|
||||
|
|
|
|||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue